Programmable Phase Delay Circuit for Asynchronous Signal Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital electronic circuits face challenges in processing signals with unknown phase relationships, leading to errors and inefficiencies due to the need for a common clock signal to govern phase relationships among various circuits, limiting individual circuit speeds and increasing power consumption.
Innovation Solution
A circuit and method that generate and set a programmable delay between two signals with unknown phase relationships by using a phase signal generator, phase select logic, and a second signal generator, allowing asynchronous operation of sub-systems without a common clock, enabling local synchronization only where needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock signal is used to govern phase relationships among various circuits, then signals have a known phase relationship enabling accurate sampling, but individual circuit speeds are limited to the lowest-common-denominator speed and power consumption increases
Solution Approach 1:
The system segments the clock distribution by allowing different circuits to use signals with different phase offsets from the same source, rather than forcing all circuits to use a single common clock. This enables each circuit to operate at its optimal speed while maintaining reliable phase relationships through the delay tracking mechanism.
Solution Approach 2:
The system changes the parameter of phase offset by allowing it to vary between different signal paths while maintaining a known relationship through tracking. The delay between signals is made programmable and adjustable, enabling optimization for different circuit speed requirements while preserving sampling accuracy.
2Reliability
If a common clock signal is distributed to the entire system to define phase relationships, then signals can be processed reliably, but the system must operate at the lowest-common-denominator speed determined by the slowest circuit
Solution Approach 1:
The system introduces dynamic phase offset adjustment capability, allowing the phase relationship between signals to be dynamically configured based on the specific requirements of different circuit pairs. This enables faster circuits to operate at higher speeds while slower circuits receive appropriately delayed signals, eliminating the lowest-common-denominator speed limitation.
3Reliability
If clock and data recovery circuits are used to recover phase information from received signals, then phase relationship is restored, but die area, power consumption, and latency increase
Solution Approach 1:
The system extracts only the essential phase tracking functionality needed for reliable signal processing, removing the bulky and power-intensive clock and data recovery circuits. By implementing a simplified delay tracking mechanism that monitors and adjusts phase offsets between signals, the system achieves phase information recovery with minimal die area and power consumption.
Data Source
AI summary
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.