Programmable Phase Delay Circuit for Unknown-Phase Periodic Signals
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Solution Overview
Problem
Digital electronic circuits face challenges in processing signals with unknown phase relationships, leading to errors and inefficiencies due to the need for a common clock signal to govern phase relationships among various circuits, limiting individual circuit speeds and increasing power consumption.
Innovation Solution
A circuit and method that generate a programmable delay between two signals with unknown phase relationships by using a phase signal generator, phase select logic, and a second signal generator, allowing asynchronous operation of sub-systems without a common clock, enabling each sub-system to operate at its optimal speed while maintaining synchronization only where needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock signal is used to govern phase relationships among various circuits, then phase synchronization is achieved, but individual circuit speeds are limited and power consumption increases
Solution Approach 1:
The patent divides the system into independent sub-systems that each generate their own clock signals from a common master signal. Instead of one global clock governing all circuits, each sub-system segments the clocking function, allowing autonomous operation while maintaining phase trackability through the delay measurement circuitry.
Solution Approach 2:
The patent changes the parameter of clock signal distribution from a single common clock to multiple derived clock signals with programmable phase delays. The delay between clock signals is made programmable and trackable, allowing phase relationships to be adjusted and monitored without requiring a shared clock source.
2Reliability
If a common clock signal is used to govern phase relationships among various circuits, then phase synchronization is achieved, but individual circuit speeds are limited
Solution Approach 1:
The patent segments the clocking architecture so that each sub-system can operate at its own optimal speed using independently derived clock signals. The segmentation allows faster circuits to run faster without being constrained by a global clock's lowest common denominator speed.
Solution Approach 2:
The patent introduces dynamic phase delay adjustment capability where the delay between clock signals can be programmably set and tracked. This dynamic parameter allows each sub-system to adapt its clock phase relationship to match its operational requirements while maintaining synchronizability when needed.
3Adaptability or versatility
If signals with unknown phase relationships are processed, then asynchronous operation is enabled, but errors are generated in sampling these signals
Solution Approach 1:
The patent implements feedback through delay measurement circuitry that continuously measures and tracks the phase delay between clock signals from different sub-systems. This feedback mechanism allows the system to detect and compensate for phase relationships, ensuring accurate sampling even when sub-systems operate asynchronously at different speeds.
Solution Approach 2:
The patent introduces an intermediary delay measurement and tracking mechanism that mediates between asynchronously operating sub-systems. This intermediary circuitry translates and tracks phase relationships, allowing signals with initially unknown phase relationships to be properly synchronized for sampling purposes.
4Reliability
If clock and data recovery circuits are used to recover phase information, then phase synchronization is achieved, but die area and power consumption increase
Solution Approach 1:
The patent uses a simplified approach that copies the master signal through programmable delay elements to generate derived clock signals with controlled phase relationships. This copying method with built-in delay tracking avoids the need for complex clock and data recovery circuits, reducing die area while maintaining phase synchronization capability.
Data Source
AI summary
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.