Programmable Phase Detector for Optical Sequence Equalizer

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Solution Overview

Problem

High-speed optical communications networks face limitations in clock recovery due to inter-symbol interference and non-linear, non-Gaussian channel noise, which restricts signal reach and link bandwidth, and existing techniques require high-speed digital circuits that increase costs and degrade performance.

Innovation Solution

A method for acquiring a channel lock condition in a direct-detection receiver using pre-computed sets of channel statistics optimized for various combinations of chromatic dispersion and polarization mode dispersion, allowing for robust clock recovery and blind acquisition, even in the presence of non-linear Gaussian noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional PLL-based clock recovery techniques are used, then the system can achieve clock recovery, but the signal reach and link bandwidth are limited due to tolerance to inter-symbol interference

Engineering Contradiction:
Improveclock recovery robustnessVSAvoidsignal reach and link bandwidth
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the fundamental parameters of clock recovery by transitioning from PLL-based methods to blind clock recovery using digital sequence estimation. This involves changing the noise model assumptions from linear Gaussian to non-linear non-Gaussian, and using different statistical methods (MLSE, MAP, Turbo-decoding) to achieve robust clock recovery without being limited by inter-symbol interference tolerance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the traditional PLL mechanical feedback system with a digital signal processing approach using blind clock recovery. Instead of using phase-locked loop circuits that require accurate symbol timing, the invention uses digital sequence estimation techniques that can operate without prior knowledge of symbol timing, substituting analog/mixed-signal PLL mechanisms with purely digital processing

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If Godard clock recovery techniques are used, then the acquisition range is improved, but the heat generation increases and system performance degrades at line rates above 20 Gbaud

Engineering Contradiction:
Improveacquisition rangeVSAvoidheat generation
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent implements dynamic adaptability by providing multiple sets of channel statistics that can be selected based on different optical channel conditions (chromatic dispersion and polarization mode dispersion combinations). The system dynamically switches between pre-computed channel statistics sets to optimize performance for varying line rates and channel conditions, allowing robust operation from low to high speeds without the fixed T/2 sampling requirement of Godard methods

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the sampling and processing parameters adaptively by using blind clock recovery that doesn't require fixed T/2 spaced sampling. Instead, the system uses multiple channel statistics sets with different parameters optimized for various dispersion conditions, allowing flexible operation across different line rates without the heat-generating high-speed digital circuits required by Godard's fixed sampling approach

Inventive Principle:
Principle #35Parameter changes

3Reliability

If T/2 spaced sampling is used in Godard clock recovery, then the clock recovery can be achieved, but the sample rate must be double the signal line rate which increases circuit complexity and cost

Engineering Contradiction:
Improveclock recovery functionalityVSAvoiddigital circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-computing multiple sets of channel statistics for different combinations of chromatic dispersion and polarization mode dispersion before operation. These pre-computed statistics are stored and selectively applied during operation, eliminating the need for real-time high-speed digital signal processing and T/2 spaced sampling, thus reducing circuit complexity while maintaining clock recovery functionality

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating multiple pre-computed copies of channel statistics for different channel conditions. Instead of requiring complex real-time processing, the system copies the appropriate pre-computed channel statistics set that matches the current channel conditions and applies it directly, simplifying the operational complexity while achieving reliable clock recovery

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8180228B1Programmable phase detector for sequence equalizer for optical channels
Publication Date: 2012.05.15 CIENA CORP
  • US8180228B1 patent drawing
  • US8180228B1 patent drawing
  • US8180228B1 patent drawing

AI summary

In a direct-detection receiver having an analog-to-digital converter (ADC) for sampling a received optical signal and a sequence estimator for recovering data symbols from a multi-bit sample stream generated by the ADC, a method of acquiring a channel lock condition of a clock recovery block of the receiver. A plurality of sets of channel statistics are provided. Each set of channel statistics optimizes performance of the sequence estimator for a respective predetermined combination of channel chromatic dispersion and polarization mode dispersion. At least one set of channel statistics will, when installed in the sequence estimator, yield symbol estimates having residual distortions that are within an acquisition range of the clock recovery block. During start-up of the receiver, one of the sets of channel statistics is selected and installed in the Sequence Estimator. If a channel lock condition is not detected within a predetermined time interval, the step of selecting one of the sets of channel statistics and installing the selected set of channel statistics in the Sequence Estimator is repeated until a channel lock condition is detected.