Programmable Photonic Tiles for Low-Power High-Bandwidth Chip Links
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Solution Overview
Problem
Modern computing systems face scalability limitations due to power consumption, thermal issues, and bandwidth constraints, particularly in inter-chip and intra-chip communications, with existing electrical interconnects being power-hungry and bandwidth-limited.
Innovation Solution
The use of photonic interposers with programmable photonic tiles and optical connections, enabling low-power, high-bandwidth communication between chips and memory, allowing for flexible network topologies and efficient integration of heterogeneous technologies on a single wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrical interconnects are used for chip communication, then ease of manufacture is improved, but power consumption increases and bandwidth is limited
Solution Approach 1:
The patent replaces electrical interconnects with optical waveguides for signal transmission. The electrical signals are converted to optical signals using modulators coupled to the waveguides, enabling photonic communication that consumes less power and provides higher bandwidth while maintaining manufacturability through standard semiconductor fabrication processes
Solution Approach 2:
The patent introduces photonic transceivers as intermediary components that convert electrical signals to optical signals and back. These transceivers include modulators that modulate light carriers with electrical signal information and detectors that convert optical signals back to electrical signals, enabling efficient electrical-optical-electrical communication
2Ease of manufacture
If electrical interconnects are used for chip communication, then ease of manufacture is improved, but communication bandwidth is limited
Solution Approach 1:
The patent substitutes electrical signal transmission through metal interconnects with optical signal transmission through waveguides. This substitution enables significantly higher communication bandwidth due to the higher frequency of optical carriers, while the waveguides can be fabricated using standard semiconductor processes
Solution Approach 2:
The patent implements programmable photonic circuits with reconfigurable waveguide connections that can dynamically adjust communication paths and bandwidth allocation. The programmable nature allows the system to adapt bandwidth resources based on real-time communication demands
3Use of energy by moving object
If photonic interposers are used for chip communication, then power consumption is reduced and bandwidth is increased, but device complexity increases
Solution Approach 1:
The patent employs a template-based photonic tile design where a single photonic circuit template can be instantiated multiple times to create different photonic interposers. This templating approach reduces design complexity by providing a reusable, standardized building block that can be configured for various applications through parameter adjustment rather than complete redesign
Solution Approach 2:
The patent divides the photonic interposer into discrete, modular photonic tiles that can be independently designed, fabricated, and assembled. Each tile contains standardized components (transceivers, waveguides, couplers) that can be combined in different configurations, reducing overall system complexity through modularity
4Loss of time
If photonic interposers are used for chip communication, then communication latency is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses identical template photonic circuits that are replicated across multiple tiles. This copying approach ensures that all tiles have the same optimized signal path lengths and coupling characteristics, reducing variability and ensuring consistent low-latency performance across the entire photonic interposer
Solution Approach 2:
The patent optimizes waveguide geometry parameters (width, height, spacing) and coupling parameters to minimize signal transmission time and maximize coupling efficiency. By carefully controlling these physical parameters during fabrication, the system achieves low-latency communication while working within standard manufacturing precision capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The photonic interposers provide low-latency, high-bandwidth communication, address thermal constraints, and enable scalable computing architectures by integrating diverse chips with efficient memory access and reduced overhead, enhancing performance and energy efficiency.
Implementation Method 1
each programmable interconnection comprises a waveguide crossing and an active coupler
Implementation Method 2
the first waveguide is evanescently coupled with the second waveguide and the second waveguide is evanescently coupled with the third waveguide
Implementation Method 3
The transceiver comprises a plurality of modulators, coupled to a first bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another; and a plurality of drop filters, coupled to a second bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another
Implementation Method 4
tuned at different wavelengths relative to one another
Implementation Method 5
each of the plurality of photonics tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter
Implementation Method 6
the first and second outputs of the interferometer are coupled to the resonant filter
Data Source
AI summary
Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.