Programmable Pin Assignment for Multi-Core Embedded Devices
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Solution Overview
Problem
Existing multi-processor core devices lack flexibility in assigning external pins to various embedded peripherals, leading to inefficiencies in pin utilization and potential interference between processor cores.
Innovation Solution
Implementing a Peripheral Pin Selection (PPS) module for each processor core, allowing programmable assignment of external pins to specific peripheral devices, with exclusive memory access and ownership logic to prevent interference, enabling flexible pin assignment and protection from inadvertent core interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a high pin count package is used to provide increased flexibility in pin assignment, then pin assignment flexibility is improved, but device complexity and cost increase
Solution Approach 1:
The patent divides the pin assignment control into separate PPS modules for each processor core. Each core has its own dedicated PPS module that can independently configure pin assignments for peripherals associated with that core, eliminating the need for a single complex centralized pin management system and reducing overall device complexity while maintaining flexibility.
Solution Approach 2:
The patent implements local pin assignment control where each processor core has dedicated control over pin assignments for its associated peripherals. This localized approach allows each core to independently manage its pin configurations without interfering with other cores, providing flexibility while simplifying the overall control architecture through distribution of functionality.
2Productivity
If external pins are shared among multiple processor cores, then pin utilization efficiency is improved, but interference between processor cores increases
Solution Approach 1:
The patent introduces an ownership logic mechanism that acts as an intermediary between multiple processor cores sharing external pins. This ownership logic tracks which core currently owns or has priority access to each shared pin, preventing simultaneous conflicting accesses and eliminating interference while maintaining efficient pin utilization through controlled sharing.
Solution Approach 2:
The patent implements preliminary assignment of pin ownership to processor cores before shared access occurs. By pre-establishing ownership relationships and access priorities, the system prevents interference before it can occur, allowing efficient pin sharing while maintaining clear control boundaries between cores.
3Adaptability or versatility
If peripheral pin selection modules are made programmable by any processor core, then pin assignment flexibility is improved, but unintended interference between cores increases
Solution Approach 1:
The patent makes PPS modules programmable only by their associated processor core, creating localized control authority. Each core can programmatically configure pins for its peripherals through its dedicated PPS module, providing flexibility for that core while the ownership logic prevents other cores from inadvertently interfering with those pin assignments.
Solution Approach 2:
The ownership logic serves as an intermediary that mediates access between processor cores and PPS modules. It ensures that only the owning core can programmatically modify pin assignments for its peripherals, maintaining reliability by preventing inadvertent interference while preserving flexibility for authorized configuration.
Data Source
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AI summary
An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.