Programmable Pipeline Interface for Hardened Blocks
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Solution Overview
Problem
Transmitting data between programmable logic (PL) and hardened blocks in programmable integrated circuits (ICs) is challenging due to increasing clock speeds and clock skew, which complicates meeting timing demands and requires efficient routing strategies to mitigate latency and uncertainty in data transfer.
Innovation Solution
A programmable pipeline with a sequential element and a bypass path is used to communicate between PL fabric and hardened blocks, allowing for dynamic configuration based on timing requirements, where time-critical nets route through the sequential element and non-critical nets bypass it, thereby optimizing data transfer and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock speed is increased to improve performance, then processing speed is improved, but timing closure becomes more difficult
Solution Approach 1:
The data path between hardened blocks and PL fabric is segmented into multiple pipeline stages with sequential elements. This segmentation allows the system to operate at higher clock speeds by breaking down complex timing requirements into smaller, manageable stages, where each stage can be independently timed and optimized.
Solution Approach 2:
Sequential elements are introduced as intermediary components between hardened blocks and PL fabric. These intermediaries buffer and synchronize data transfers, absorbing timing variations and clock skew effects, thereby enabling reliable data transmission even at increased clock speeds.
2Reliability
If data is routed through sequential elements to meet timing requirements, then timing closure is improved, but latency increases
Solution Approach 1:
The routing configuration is made dynamic and adaptable. The system can selectively enable or disable sequential elements in the data path based on timing requirements. For non-critical paths, sequential elements can be bypassed to minimize latency, while for critical paths, they are activated to ensure timing closure.
Solution Approach 2:
The system allows changing of routing parameters and pipeline stage configurations based on specific timing requirements. By adjusting which sequential elements are active and how data is routed through the pipeline, the system optimizes the balance between timing closure and latency for different data paths.
3Reliability
If a fixed routing path is used for data transfer, then timing predictability is improved, but adaptability decreases
Solution Approach 1:
The interface circuitry is designed with multi-functional capability. The same physical infrastructure (interconnects, sequential elements) can be configured to serve multiple routing purposes. This universality allows the system to provide fixed, predictable routing paths when needed while maintaining the flexibility to reconfigure for different adaptability requirements.
Solution Approach 2:
The routing configuration can be dynamically adjusted based on timing analysis. The system determines which paths require fixed routing for timing predictability and which can utilize more flexible routing options, allowing optimal configuration for each specific data transfer scenario.
Data Source
AI summary
Embodiments herein describe an interface between PL fabric and a hardened block that includes a programmable pipeline. This pipeline includes at least a sequential element and a bypass path. For time critical nets in a netlist, the programmable IC routes a net through the sequential element. Doing so mitigates or eliminates the uncertainty associated with routing the net from the hardened block through PL fabric. Also, the sequential element can increase the available time for capturing the data. For less time critical nets, the net can route through the bypass path. This means the route from the hardened block to the PL fabric is determined on the fly by a routing algorithm rather than being fixed.