Programmable PLL Bandwidth Switching for Low-Glitch Clock Handover
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In optical communication systems, phase-locked loops (PLLs) face challenges in implementing low-bandwidth PLLs for hitless switching between input reference clocks, as they are difficult to implement in monolithic integrated circuits, expensive, and result in increased jitter and slow lock times, failing to meet tight phase transient requirements.
Innovation Solution
A programmable PLL with selectable bandwidth and frequency, configured using stored sets of configuration information based on the selected frequency and bandwidth, allowing for precise adjustment of PLL parameters to minimize phase glitches during switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLL bandwidth is reduced to achieve hitless switching between input clocks, then phase transient requirements are met, but the PLL achieves lock slowly and generates increased jitter
Solution Approach 1:
The patent applies dynamics by making the PLL bandwidth adjustable rather than fixed. The system can dynamically switch between different bandwidth settings: a narrow bandwidth during normal operation to minimize jitter, and a wider bandwidth during acquisition/locking to speed up the locking process. This resolves the contradiction by allowing the system to optimize for different operational states.
Solution Approach 2:
The patent changes the bandwidth parameter of the PLL based on operational requirements. By providing multiple bandwidth options (e.g., through selectable filter configurations or programmable gain amplifiers), the system can adjust the bandwidth parameter to achieve fast locking when needed while maintaining low jitter during steady-state operation, thus resolving the trade-off between lock time and jitter performance.
2Reliability
If a low-bandwidth PLL is used to meet tight phase transient requirements, then phase glitches are reduced, but the implementation becomes difficult in monolithic integrated circuits and increases cost
Solution Approach 1:
The patent segments the filtering function into multiple stages rather than relying on a single low-bandwidth PLL. By using a cascade of filters or a multi-stage approach, the system can achieve the equivalent of a very low bandwidth without requiring an impractically low single-stage bandwidth, making the design more implementable in standard integrated circuit processes.
Solution Approach 2:
The patent introduces additional circuitry (such as digital signal processing blocks, Sigma-Delta modulators, or intermediate filtering stages) that act as intermediaries to achieve the desired phase transient performance without requiring the main PLL to operate at impractically low bandwidths. This allows the core PLL to maintain reasonable bandwidth for manufacturability while the intermediary components handle the tight phase transient requirements.
3Reliability
If the PLL bandwidth is reduced to minimize phase movement, then transmission errors are reduced, but the output clock jitter increases due to reduced filtering
Solution Approach 1:
The patent uses dynamic bandwidth adjustment where the PLL operates with a narrow effective bandwidth during switching events to minimize phase movement and transmission errors, but can widen its bandwidth during normal operation to maintain low jitter. This dynamic adaptation resolves the contradiction by optimizing the bandwidth for the current operational context.
Solution Approach 2:
The patent employs periodic resetting or recalibration mechanisms that allow the PLL to temporarily accept higher jitter during brief intervals (such as during controlled switching events) while maintaining low jitter performance during the majority of operation. The periodic nature of these events allows the system to tolerate occasional jitter spikes while maintaining overall transmission reliability.
Data Source
AI summary
A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.