Programmable PMU Processor for Software-Defined Monitoring
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Solution Overview
Problem
Current PMU architectures in processors have fixed designs, limiting their ability to adapt to diverse requirements and allowing only limited sharing of PMU resources among software processes, which results in resource contention and reduced accuracy in data collection.
Innovation Solution
A programmable PMU processor that can be dynamically programmed by software processes to add new PMU events and share resources, managed by an OS-based PMU driver to enable concurrent data collection without conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PMU architecture uses fixed design in processor circuitry, then device complexity is reduced and manufacturing is easier, but adaptability to diverse requirements cannot be achieved
Solution Approach 1:
The patent implements a dynamically reconfigurable PMU architecture using FPGA technology, allowing the PMU circuitry to be reprogrammed and reconfigured after manufacturing. This enables the system to adapt to diverse monitoring requirements by dynamically changing the PMU's functional behavior without physical hardware changes, resolving the contradiction between fixed design simplicity and adaptability needs.
Solution Approach 2:
The patent changes the operational parameters of the PMU through software configuration and reprogramming of the FPGA-based PMU logic. By modifying configuration parameters, event types, and monitoring thresholds through software rather than hardware changes, the system achieves high adaptability while maintaining a relatively simple base hardware architecture.
2Productivity
If PMU resources are shared among multiple software processes, then resource utilization improves, but resource contention and conflicts occur reducing data collection accuracy
Solution Approach 1:
The patent segments PMU resources into multiple independent counter sets, each capable of being independently allocated to different software processes. The FPGA-based PMU architecture provides multiple parallel counting channels that can be simultaneously assigned to different processes, eliminating resource contention while maintaining high resource utilization and ensuring accurate data collection for each process.
Solution Approach 2:
The patent introduces an intermediary resource manager component that mediates between multiple software processes and the PMU hardware resources. This intermediary manages resource allocation, coordinates access to PMU counters, and prevents conflicts by ensuring proper synchronization and arbitration, thereby maintaining both high resource utilization and data collection accuracy.
3Adaptability or versatility
If more PMU events are added for specialized use cases, then versatility increases, but fixed PMU architecture cannot accommodate new events without upgrading processor circuitry
Solution Approach 1:
The patent implements a universal PMU event encoding scheme where a single PMU counter can monitor multiple different event types through software-configurable event selection. The FPGA-based architecture allows the same hardware resource to be dynamically reconfigured to monitor various specialized events (cache misses, branch predictions, memory accesses, etc.) by changing software parameters rather than adding dedicated hardware counters for each event type, thereby achieving high versatility without increasing manufacturing complexity.
Data Source
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AI summary
A processor includes one or more processing cores, and a performance monitoring unit (PMU), the PMU including one or more performance monitoring counters; a PMU memory to store a PMU kernel, the PMU kernel including one or more programmable PMU functions; and a PMU processor to load the PMU kernel and concurrently execute the one or more programmable PMU functions of the PMU kernel to concurrently access the one or more performance counters.