Programmable Power Rail Sequencing for Changing IC Requirements
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Solution Overview
Problem
Current hardware-based line cards face inefficiencies and high costs due to the complexity of power and control sequencing requirements for various Integrated Circuits (ICs), which often necessitate manual implementation of discrete circuits and redesigns with component changes.
Innovation Solution
A programmable sequencer, such as a Complex Programmable Logic Device (CPLD) or Field Programmable Gate Array (FPGA), that receives stimulus signals to generate control signals for initializing power rails in a specified order, allowing for efficient and dynamic power rail sequencing without requiring modifications to underlying circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual implementation of discrete circuits is used to meet sequencing requirements, then power rail sequencing can be achieved, but the process becomes time-consuming and expensive requiring redesign whenever components change
Solution Approach 1:
The patent implements a universal power rail sequencing controller that can manage multiple power rails with different sequencing requirements through a single programmable device. The controller receives identification signals for multiple power rails and generates corresponding control signals, eliminating the need for separate discrete circuits for each power rail while maintaining reliable sequencing.
Solution Approach 2:
The patent uses programmable parameters to define sequencing requirements. The controller can be reconfigured by loading different instruction sets that specify timing parameters, activation orders, and control signal characteristics. This allows the system to adapt to different component requirements without hardware redesign, resolving the contradiction between reliability and device complexity.
2Reliability
If hardware engineers manually implement discrete circuits for each line card configuration, then sequencing requirements can be met, but the process becomes inefficient and costly
Solution Approach 1:
The patent implements a self-configuring system where the power rail sequencing controller automatically identifies power rails through identification signals and generates appropriate control signals without manual intervention. The controller loads instruction sets that define sequencing parameters, enabling the system to configure itself automatically and eliminating time-consuming manual circuit implementation.
Solution Approach 2:
The patent replaces manual mechanical implementation of discrete circuits with an automated electronic control system. The programmable controller uses electronic instruction sets to define sequencing behavior, substituting the manual mechanical process of circuit implementation with an automated electronic configuration process that is both faster and more reliable.
3Adaptability or versatility
If different ICs with different power and control sequencing requirements are used, then line card functionality increases, but the sequencing complexity increases requiring frequent redesigns
Solution Approach 1:
The patent implements a dynamic sequencing controller that can adapt its behavior based on real-time conditions. The controller receives identification signals from different ICs and power rails, loads appropriate instruction sets, and generates control signals dynamically. This dynamic adaptability allows the system to handle diverse IC requirements without increasing hardware complexity, as the controller reconfigures itself based on the specific components present.
Data Source
AI summary
A power sequencing method may use a state machine in a programmable sequencer to program relative timing of signals to activate different power rails attached to an integrated circuit. Input lines may specify the sequencing program. Alternatively, the programmable sequencer may use an EEPROM or other computer-readable medium to program itself with a particular image of the sequencing program. The programmable sequencer may be implemented by a Field Programmable Gate Array (FPGA).