Programmable PRBS Generator for DRAM Training
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Solution Overview
Problem
Conventional pseudo random bit stream generators for memory systems, such as DRAM, face challenges in generating optimal data eye positioning due to limited flexibility and increased circuit area requirements as memory speeds rise, especially with high-frequency loss and inter-symbol interference issues.
Innovation Solution
A programmable parallel pseudo random bit stream generator with fully programmable polynomial, tap selection, and parallel sequence generation capabilities, utilizing a state-bits generator circuit block and tap selection circuit blocks with control status registers to dynamically generate pseudo random training patterns for improved data eye positioning and reduced circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fixed function LFSR circuits are used to generate random data patterns, then hardware training mechanisms can provide good control precision, but the circuits require significant circuit area and have limited flexibility
Solution Approach 1:
The patent implements dynamic configurability by allowing the LFSR circuits to be reconfigured through control signals. The tap selection logic can be programmed to select different feedback taps and connection configurations, enabling the same hardware to adapt to different PRBS polynomial requirements without physical redesign, thus resolving the contradiction between fixed precision and adaptive flexibility
Solution Approach 2:
The invention changes the operational parameters of the LFSR circuits by introducing programmable tap selection mechanisms. By allowing dynamic modification of which taps are active and how they are connected through control logic, the system can adjust its behavior to match different training requirements while maintaining the same physical circuit structure
2Reliability
If the number of PRBS generator circuits increases with the number of DRAM data lanes, then each lane can be trained independently, but the circuit area increases significantly
Solution Approach 1:
The patent implements a universal PRBS generator architecture where a single reconfigurable circuit can serve multiple DRAM data lanes. By implementing programmable tap selection and control logic that can be configured through software or control signals, one physical generator can generate the required PRBS sequences for any number of lanes by changing its internal configuration, eliminating the need for dedicated hardware per lane
Solution Approach 2:
The invention merges multiple PRBS generator functions into a single integrated circuit block. By combining the LFSR logic, tap selection mechanisms, and control interfaces into one reconfigurable unit, the system achieves the functional equivalent of multiple independent generators while using significantly less physical space
Data Source
AI summary
A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.