Programmable Priority Logic Module for Faster Nuclear Certification
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Solution Overview
Problem
Nuclear process control systems face challenges in efficiently managing and certifying priority logic modules due to the need for extensive and costly testing across various environmental and operational conditions, which is time-consuming and resource-intensive, especially when priority logic changes are required.
Innovation Solution
Implementing a priority logic module using a complex programmable logic device (CPLD) that allows for reprogramming to support different priority logic functionalities without requiring extensive retesting, while also being designed to prevent field reprogramming and comply with stringent nuclear safety standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a priority logic module is implemented with fixed logic circuitry to ensure reliability and safety in nuclear control systems, then the system meets safety standards and operates reliably, but any changes to priority logic require extensive retesting and recertification across all environmental and operational conditions, which is time-consuming and resource-intensive
Solution Approach 1:
The patent implements a programmable logic device that can be configured with different priority logic functionalities through programming rather than hardware changes. A single certified device platform supports multiple priority logic configurations, eliminating the need for separate certification of each specific logic implementation. This universal approach maintains safety and reliability while dramatically reducing certification time for logic changes.
Solution Approach 2:
The patent changes the physical state or configuration parameter of the logic device from fixed hardware circuitry to programmable logic. By using a programmable logic device with inhibited field reprogramming capability, the system allows logic changes through programming in controlled environments while maintaining safety certification. This parameter change enables flexible logic modification without requiring extensive retesting and recertification.
2Reliability
If a priority logic module is implemented with fixed logic circuitry to ensure safety and reliability, then the system operates reliably, but changes to priority logic are difficult and require extensive retesting and recertification
Solution Approach 1:
The programmable logic device serves multiple functions by implementing different priority logic configurations through programming. A single device platform can be programmed with various priority logic schemes depending on operational requirements, providing adaptability while maintaining the safety and reliability of the certified hardware platform.
Solution Approach 2:
The patent introduces dynamic reconfigurability through programmable logic devices that can be programmed in controlled environments. The inhibited field reprogramming capability ensures that changes occur only under controlled conditions, maintaining safety while enabling adaptability when needed. This dynamic approach allows the system to adjust priority logic without compromising reliability.
3Adaptability or versatility
If a programmable logic device is used to allow reprogramming of priority logic, then adaptability and ease of reprogramming are improved, but there is a risk of unauthorized or erroneous field reprogramming that could compromise safety
Solution Approach 1:
The patent applies preliminary anti-action by inhibiting field reprogramming capability before the device is deployed to the field. The programmable logic device is configured to prevent any reprogramming attempts in the field environment, thereby preemptively protecting against unauthorized or erroneous changes that could compromise safety. This preliminary protective measure maintains safety assurance while allowing controlled reprogramming in manufacturing or testing environments.
Solution Approach 2:
The patent introduces an intermediary mechanism (inhibited reprogramming capability) that mediates between the need for adaptability and safety assurance. This intermediary allows programming in controlled environments while blocking programming in field conditions, thus enabling ease of reprogramming where needed while maintaining safety assurance where required.
4Reliability
If extensive testing is performed across various environmental and operational conditions to certify priority logic changes, then safety and reliability are ensured, but the process becomes time-consuming and resource-intensive
Solution Approach 1:
The patent uses a universal certified device platform that can implement multiple priority logic configurations. Once the hardware platform is certified for safety and reliability, different logic functionalities can be programmed without requiring separate extensive testing for each logic configuration. This significantly improves certification efficiency while maintaining safety assurance through the inherited hardware certification.
Solution Approach 2:
The patent performs preliminary certification of the hardware platform before deployment. This preliminary action establishes the safety and reliability baseline, allowing future logic changes to be implemented through programming without requiring repeated extensive environmental and operational testing. This preliminary certification improves productivity while maintaining reliability.
Data Source
AI summary
In a nuclear process control system, a priority logic module (PLM) is provided. The priority logic module comprises a plurality of input ports, each input port associated with one of a plurality of priorities, a plurality of output ports, and a test mode select port associated with a test mode select signal. The test mode select signal selects one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports. The priority logic module further comprises a configurable priority logic circuit, wherein the priority logic circuit maps one of the input ports to one of the output ports.


