Programmable Processor in Integrated Memory Assembly
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Solution Overview
Problem
Existing memory systems with hard-wired state machines are inflexible and costly to modify, making it difficult to adapt to new design requirements or improve performance, especially when interference from neighboring memory cells is discovered after fabrication, and bit error rates across pages are not evenly distributed.
Innovation Solution
A programmable and reprogrammable processor on a control semiconductor die that can control memory operations, allowing for updates in instruction sets to modify voltage timing and magnitude, page mapping schemes, and sense amplifier operations, enabling efficient communication and adaptation to changing conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a hard-wired state machine is used to control memory operations, then the memory structure can be fabricated with fixed control logic, but the system becomes inflexible and costly to modify when design changes or performance improvements are needed
Solution Approach 1:
The patent replaces the static hard-wired state machine with a dynamic processor that can execute different instruction sets. The control logic transitions from being physically fixed during fabrication to being programmatically configurable, allowing the same hardware to adapt its behavior through software updates without requiring physical re-engineering.
Solution Approach 2:
The invention changes the control parameters from fixed hardware wiring to modifiable instruction sets and configuration data. By storing control logic as programmable instructions rather than hard-wired circuits, the system can modify its operational parameters (voltage timing, sense amplifier control, page mapping) through software rather than hardware changes.
2Device complexity
If voltage timing and magnitude are fixed in hard-wired control logic, then manufacturing is simpler, but performance optimization and interference compensation are difficult
Solution Approach 1:
The control logic dynamically adjusts voltage timing and magnitude based on executed instructions rather than being statically fixed. This allows the system to optimize voltage parameters for different memory operations and compensate for interference patterns discovered after fabrication, improving reliability without permanently increasing hardware complexity.
Solution Approach 2:
The processor can implement feedback mechanisms where voltage parameters are adjusted based on observed performance and error patterns. By monitoring memory operation outcomes and using that information to modify subsequent voltage timing and magnitude through updated instructions, the system compensates for interference and improves error distribution across pages.
3Ease of manufacture
If the control logic is hard-wired, then initial manufacturing cost is lower, but any modifications require costly re-engineering
Solution Approach 1:
Instead of physically copying and re-wiring control logic for modifications, the system copies instructions through software loading and updates. The processor can load new instruction sets from external sources or internal storage, enabling modifications without physical re-engineering while maintaining the simplicity of the original fabrication process.
Solution Approach 2:
The control system transitions from static hard-wired logic to dynamic programmable logic, where modifications are achieved through software updates rather than hardware re-engineering. This maintains low initial fabrication costs while dramatically reducing modification costs through the ability to reprogram the processor with new instruction sets.
4Device complexity
If page mapping schemes are fixed in hardware, then the control structure remains simple, but adapting to changing conditions and improving error distribution is impossible
Solution Approach 1:
Page mapping schemes transition from fixed hardware configurations to dynamic software-controlled mappings. The processor can execute different page mapping algorithms and adjust mapping strategies based on observed error patterns and performance metrics, allowing adaptation to changing conditions without increasing fundamental control structure complexity.
Solution Approach 2:
The page mapping parameters are changed from fixed hardware settings to modifiable software instructions. This allows the system to adjust page mapping schemes to distribute errors more evenly across pages and adapt to changing memory conditions through updated instruction sets rather than hardware reconfiguration.
Data Source
AI summary
A programmable and reprogrammable processor on a control semiconductor die is disclosed. The processor controls various operations on a memory semiconductor die to which it is bonded, such as read, write, and erase. The processor issues control signals to operate circuits such as voltage regulators, sense amplifiers, and data latches. Because the processor is reprogrammable, it is possible to modify the operation of the circuits. For example, the processor can execute updated instructions to control the voltage regulators to modify the timing and/or magnitude of voltages applied to control lines in the memory semiconductor die. In one aspect, a page mapping scheme is updated in order to more evenly distribute a bit error rate (BER) across the pages. In one aspect, a read equalization scheme is updated. In one aspect, a technique for reading soft bits is updated.