Programmable Protocol Generator for Semiconductor Device Testing

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Solution Overview

Problem

Current semiconductor device testers lack efficient programmable hardware configurations to effectively control data flow and execute operation codes for comprehensive testing of semiconductor devices, limiting their ability to perform complex data transactions and validation processes.

Innovation Solution

The implementation of programmable hardware with dual pattern generators, a transmit pattern generator, and a receive pattern generator, which communicate to control data flow to and from semiconductor devices under test, allowing for the execution of operation codes and synchronization of data transmission and reception.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a single pattern generator is used to generate signals for the DUT, then the device complexity is reduced, but the ability to control data flow and execute operation codes is limited

Engineering Contradiction:
Improveability to control data flow and execute operation codesVSAvoidhardware configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The pattern generator is divided into two separate functional units: a transmit pattern generator for sending data to the DUT and a receive pattern generator for receiving and processing data from the DUT. This segmentation allows each unit to be optimized for its specific function while maintaining overall system versatility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Both the transmit and receive pattern generators are programmed with operation codes that enable them to perform multiple functions. The transmit pattern generator can execute operations specifying data to be transmitted, while the receive pattern generator can execute operations against received data, making the system adaptable to various testing scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If programmable hardware with dual pattern generators is implemented, then testing efficiency and validation capability are improved, but the device complexity increases

Engineering Contradiction:
Improvetesting efficiencyVSAvoidprogrammable hardware configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The receive pattern generator sends messages to the transmit pattern generator indicating when data has been received and processed. This feedback mechanism enables automatic coordination between transmission and reception operations, improving testing efficiency without requiring complex external control logic.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The transmit pattern generator is programmed with operation codes in advance that specify the data to be transmitted. This preliminary programming allows the system to execute complex testing sequences efficiently without real-time intervention, boosting productivity.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If the transmit pattern generator waits for signals from the receive pattern generator, then data flow synchronization is improved, but the speed of data transmission may be reduced

Engineering Contradiction:
Improvedata flow synchronizationVSAvoiddata transmission speed
Core Design Contradiction:
Stability of the object's compositionVSSpeed

Solution Approach 1:

The transmit and receive pattern generators operate in a continuous coordinated manner. While the transmit generator waits for acknowledgment messages from the receive generator, it maintains readiness to immediately transmit the next data set, ensuring continuous useful action without unnecessary idle time.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentEP2449391B1Programmable protocol generator
Publication Date: 2016.07.13 TERADYNE INC
  • EP2449391B1 patent drawingFigure 1
  • EP2449391B1 patent drawingFigure 2
  • EP2449391B1 patent drawingFigure 3

AI summary

A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test.