Programmable Ramp Signal Generator for Power Converters
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Solution Overview
Problem
Conventional ramp signal generators in power converters suffer from low resolution, leading to stability issues and steady-state oscillations, particularly when the ADC resolution is higher than the DAC resolution, limiting control precision and increasing the cost of implementing higher resolution DACs.
Innovation Solution
Introducing a delay in the start of the DAC's clocking process, allowing it to transition to the next state after a fixed number of clock pulses and delaying its output by fewer pulses, effectively increasing the ramp resolution without requiring a higher resolution DAC, and allowing for software programmability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional DAC-based ramp signal generator is used, then the circuit implementation is simple, but the ramp resolution is limited to the maximum DAC resolution
Solution Approach 1:
The patent segments the DAC clocking process into two independent controllable parts: (1) the number of clock pulses to transition to the next state, and (2) the delay of the output signal. This segmentation allows the system to achieve higher effective resolution by controlling these two parameters independently, without requiring a higher-resolution DAC hardware.
Solution Approach 2:
The patent introduces a time-domain dimension to the resolution problem by delaying the DAC output for a programmable number of clock pulses. This temporal dimension allows the system to generate intermediate ramp values between consecutive DAC states, effectively increasing resolution without adding spatial complexity to the DAC structure.
2Measurement precision
If the ADC resolution is higher than the DAC resolution, then measurement precision is improved, but stability issues and sub-harmonic oscillations occur due to insufficient ramp resolution
Solution Approach 1:
The patent implements a feedback mechanism where the delayed DAC output is compared with the current ramp signal, and the difference is used to adjust the timing control. This feedback ensures that the effective ramp resolution matches the ADC resolution, eliminating the mismatch that causes sub-harmonic oscillations and instability in peak current mode control.
Solution Approach 2:
The patent dynamically changes the delay parameter (number of clock pulses to delay the output) based on the operating conditions and required resolution. By programmably adjusting this parameter, the system adapts the ramp resolution to match the ADC resolution, ensuring stability across different operating points without requiring hardware changes.
3Measurement precision
If a higher resolution DAC is used to increase ramp resolution, then measurement precision is improved, but the cost and device complexity increase
Solution Approach 1:
Instead of using a physically larger high-resolution DAC, the patent creates virtual high-resolution steps by copying and timing-controlling the standard DAC output. The delay mechanism effectively creates intermediate copies of the DAC states in the time domain, achieving high resolution at low cost through temporal multiplexing rather than spatial expansion.
Solution Approach 2:
The patent changes the operational parameters of the existing DAC system (clock pulse counting and output delay) rather than changing the DAC hardware itself. By programmably adjusting these parameters, the system achieves higher effective resolution without the cost and complexity of implementing a physically higher-resolution DAC converter.
Data Source
AI summary
A system and method for controlling a power converter includes a digital-to-analog converter (DAC) and ramp generator for generating a reference current command. The DAC is configured to decrement (or increment) to a next state after a fixed number of clock pulses have occurred. The reference current command controls an output of the power converter. Means are provided for delaying an output of the DAC for a number of clock pulses less than the fixed number to increase a resolution of the DAC.