Programmable Reference Generator for DRAM Signal Margin Optimization

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Solution Overview

Problem

In dynamic random access memory (DRAM) systems, especially in silicon on insulator (SOI) eDRAM designs, the increased subthreshold leakage at high supply voltages due to floating body cell devices leads to degraded signal margins between reference and data type voltages, making it challenging to effectively sense '0' and '1' data types, and scaling the reference voltage proportionally to the power supply voltage reduces the '1' margin while improving the '0' margin.

Innovation Solution

A reference generator circuit that generates a reference voltage (VREF) as a linear function of the supply voltage (Vdd) with a nonzero y-intercept, using a mixer and buffer circuit to output a sum of fraction and DC voltages, ensuring the reference voltage is centered between signal voltages of '0' and '1' data types, thereby optimizing semiconductor device yield and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a linear voltage divider is used to generate reference voltage as a fraction of supply voltage, then the circuit complexity is reduced, but the signal margin test effectiveness is insufficient

Engineering Contradiction:
Improvereference voltage generation circuitVSAvoidsignal margin test accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent transforms the static reference voltage generation (fixed fraction from voltage divider) into a dynamic system where the reference voltage can be programmatically adjusted. The programmable parameters m and b allow the reference voltage to adapt to different operating conditions and leakage levels, enabling effective signal margin testing while maintaining reasonable circuit complexity through systematic parameter selection.

Inventive Principle:
Principle #15Dynamics

2Reliability

If higher power supply voltage is used to increase the '0' margin, then the '0' margin is improved, but subthreshold leakage increases due to floating body cell device effects

Engineering Contradiction:
Improvesignal margin for '0' data typeVSAvoidsubthreshold leakage in floating body cell device
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements a feedback mechanism where the reference voltage is programmably adjusted based on observed leakage conditions and signal margin requirements. By monitoring the operating conditions and leakage levels, the system can adjust the m and b parameters to maintain optimal reference voltage levels that compensate for leakage effects without requiring excessive supply voltage that would further increase leakage.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8773920B2Reference generator with programmable M and B parameters and methods of use
Publication Date: 2014.07.08 MARVELL ASIA PTE LTD
  • US8773920B2 patent drawing
  • US8773920B2 patent drawing
  • US8773920B2 patent drawing

AI summary

A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.