Programmable Memory Refresh Modes for Row Hammer Protection

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Solution Overview

Problem

Memory devices are vulnerable to row hammer attacks, which can corrupt neighboring memory cells due to repeated access operations, leading to increased latency and processing when multi-pump refreshes are performed unnecessarily in less vulnerable systems.

Innovation Solution

Implementing a programmable refresh configuration that allows memory devices to operate in either a single refresh mode or a multi-refresh mode based on vulnerability, using refresh configuration circuitry such as fuses or mode registers to dynamically adjust the refresh mode according to the likelihood of row hammer attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-pump refreshes are performed to protect against row hammer attacks, then security and reliability are improved, but latency and processing time increase

Engineering Contradiction:
ImprovesecurityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a configurable refresh mechanism where the refresh mode (single-pump or multi-pump) can be dynamically selected based on system vulnerability to row hammer attacks. The refresh configuration circuitry allows the system to adapt between different refresh strategies, using multi-pump refresh only when necessary to protect against attacks while using single-pump refresh for normal operations to minimize latency.

Inventive Principle:
Principle #15Dynamics

2Reliability

If multi-pump refreshes are performed continuously, then data integrity is enhanced, but processing efficiency deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the refresh operation parameter (number of pumps) based on system conditions. The refresh configuration circuitry enables selection between single-pump and multi-pump modes, allowing the system to optimize processing efficiency by using single-pump refresh when data integrity risks are low, and switch to multi-pump refresh when protection against row hammer attacks is needed.

Inventive Principle:
Principle #35Parameter changes

3Speed

If single refresh mode is used to reduce latency, then processing speed is improved, but vulnerability to row hammer attacks increases

Engineering Contradiction:
Improveprocessing speedVSAvoidvulnerability
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent implements a dynamic refresh strategy where the system can switch between single-refresh mode (for speed) and multi-refresh mode (for security) based on the assessed vulnerability to row hammer attacks. The refresh configuration circuitry enables this adaptability, allowing the system to maintain high processing speed during normal operations while providing enhanced protection when threats are detected or in high-risk environments.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250298738A1Programmable refresh configuration for memory devices
Publication Date: 2025.09.25 MICRON TECHNOLOGY INC
  • US20250298738A1 patent drawing
  • US20250298738A1 patent drawing
  • US20250298738A1 patent drawing

AI summary

Methods, systems, and devices for a programmable refresh configuration for memory devices are described. A memory system may monitor a state of refresh configuration circuitry of the memory system. The refresh configuration circuitry may be one or more fuses, mode registers, or any combination thereof. A first state of the refresh configuration circuitry may indicate that the memory system operates in a first refresh mode associated with a first quantity of refresh operations. A second state of the refresh configuration circuitry may indicate that the memory system operates in a second refresh mode associated with a second quantity of refresh operations. The memory system may receive a refresh command and may execute one or more refresh operations based on the refresh command. A quantity of refresh operations that are executed may be equal to the first quantity or the second quantity based on the state of the refresh configuration circuitry.