Programmable Circuit Reset Modes for Clock Enable Priority
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Solution Overview
Problem
Integrated circuit components often lack flexible reset and clock enable/disable capabilities, with existing components prioritizing one over the other, failing to meet design requirements for asynchronous or synchronous operations.
Innovation Solution
A circuit design that includes a first portion operating in synchronism with a clock signal and a second portion capable of operating in either asynchronous or synchronous reset modes, allowing dynamic logical value management based on control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a circuit component provides both reset and clock enable capabilities, then the component functionality is enhanced, but one of the reset or clock enable will inherently have priority over the other, limiting design flexibility
Solution Approach 1:
The circuit component dynamically switches between asynchronous and synchronous reset modes based on the state of a control signal (first control signal). When the first control signal indicates asynchronous mode, the second control signal affects the latch asynchronously; when it indicates synchronous mode, the second control signal affects the latch synchronously with the clock signal. This dynamic behavior allows the same hardware structure to provide different priority configurations without requiring multiple fixed-design components.
Solution Approach 2:
The invention changes the operational parameter of the reset function by introducing a control signal that switches between asynchronous and synchronous modes. This parameter change (from fixed asynchronous or fixed synchronous to configurable) allows the circuit to adapt to different design requirements where either reset or clock enable needs priority, resolving the contradiction between versatility and complexity.
2Adaptability or versatility
If a circuit component has fixed reset priority over clock enable, then the reset function is reliable, but the component cannot meet design requirements where clock enable needs priority
Solution Approach 1:
The circuit uses a control signal to dynamically adjust the reset function's behavior. When configured for asynchronous mode, the reset function maintains its reliable immediate effect; when configured for synchronous mode, it operates reliably with the clock cycle. The same reset circuitry adapts its timing characteristics based on control signals, ensuring reliability in both modes while providing design flexibility.
3Adaptability or versatility
If a circuit component has fixed clock enable priority over reset, then the clock control is flexible, but the component cannot meet design requirements where reset needs priority
Solution Approach 1:
The circuit dynamically adjusts the clock enable function's interaction with reset based on control signals. In asynchronous mode, the clock enable function operates with high reliability independent of reset timing; in synchronous mode, it coordinates with the clock cycle for reliable operation. This dynamic configuration allows the same hardware to provide different priority relationships between clock enable and reset functions.
Data Source
AI summary
A method and apparatus involve operating a circuit that includes a first portion and a second portion, including: operating the first portion in synchronism with a clock signal; maintaining in the first portion a logical value that can vary dynamically; and operating the second portion in a selected one of first and second operational modes. The operating of the second portion includes: responding to the occurrence of a control signal during operation in the first operational mode by causing the second portion to force the logical value in the first portion to a predetermined logical state in a manner asynchronous to the clock signal; and responding to the occurrence of the control signal during operation in the second operational mode by causing the second portion to force the logical value in the first portion to the predetermined logical state in a manner synchronized with the clock signal.