Programmable Scan Enable Circuits for Low Power IC Testing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Integrated circuit testing faces challenges with high power consumption due to excessive switching in scan chains caused by 'don't care' bits in test patterns and responses, leading to overheating and reliability issues.

Innovation Solution

The implementation of a test stimulus selector and enable circuits that selectively output either original test pattern values or constant values to reduce switching activity, using programmable controllers and multiplexers to manage control signals and enable signals on a cycle-by-cycle or pattern-by-pattern basis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If decompression hardware is used to expand compressed test patterns, then test data reduction is achieved, but excessive switching in scan chains occurs due to randomly filled don't care bits

Engineering Contradiction:
Improvetest data volumeVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent applies local quality by differentiating between specified bits and don't care bits in test patterns. Instead of treating all bits uniformly, the invention selectively controls only the specified bits that are necessary for fault detection, while leaving don't care bits in a high-impedance state. This localized approach to bit control reduces unnecessary switching activity in scan chains while maintaining test effectiveness.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by introducing dynamic control of scan chain loading. The scan chain load controller dynamically adjusts the loading of test pattern bits based on their significance - specified bits are loaded into scan chains while don't care bits are kept in high-impedance state. This dynamic control mechanism adapts the test data flow to minimize power consumption during different phases of testing.

Inventive Principle:
Principle #15Dynamics

2Reliability

If all test response bits are captured and shifted out, then complete test coverage is achieved, but excessive switching occurs in scan cells during capture and unloading

Engineering Contradiction:
Improvefault detection coverageVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies the taking out principle by extracting and removing unnecessary test response bits from the capture process. The test response controller identifies which scan chains contain meaningful test responses and which contain only don't care values. Only the necessary test responses are captured and shifted out, while responses from chains with don't care bits are excluded. This extraction of essential information reduces switching activity and power consumption during test response capture.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If high volume test data is delivered to large circuits, then comprehensive testing is achieved, but test time and tester memory requirements increase significantly

Engineering Contradiction:
Improvetest coverageVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by modifying the state of scan chain inputs during different test phases. The scan chain load controller changes the input state from active loading during test pattern application to high-impedance state during test response capture. This parameter change in the operational mode of scan chains allows the same hardware to efficiently handle both test data loading and test response capture, reducing overall test time and memory requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2122466B1Low power scan testing techniques and apparatus
Publication Date: 2015.04.29 MENTOR GRAPHICS CORP
  • EP2122466B1 patent drawingFigure 1
  • EP2122466B1 patent drawingFigure 2(a)~2(b)
  • EP2122466B1 patent drawingFigure 2(c)~2(d)

AI summary

Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures {e.g., an embedded deterministic test ("EDT") architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.