Programmable Scan-Test Circuitry for Defect Correction
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Solution Overview
Problem
Integrated circuits face challenges in detecting and correcting scan-chain defects such as hold-time violations and polarity reversals during scan testing, which are time-consuming and costly to resolve, especially when detected late in the design cycle.
Innovation Solution
Incorporating programmable circuitry with configurable memory cells to dynamically adjust signal delays and polarities within the scan chains, allowing for defect correction without requiring extensive redesign or re-routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chains are synthesized with fixed scan flip-flop cells and multiplexers, then scan testing functionality is achieved, but defects such as hold-time violations and polarity reversals occur that require costly mask revisions
Solution Approach 1:
The patent introduces programmable circuitry with configurable memory cells that can dynamically adjust the functionality of scan flip-flop cells. These cells can be programmed to compensate for hold-time violations by modifying timing characteristics and to correct polarity reversals by inverting signal logic, thereby eliminating the need for costly mask revisions while maintaining reliable scan-test functionality
Solution Approach 2:
The patent changes the parameters of scan flip-flop cells by introducing programmable delay elements and polarity correction circuitry. The delay elements can adjust timing parameters to fix hold-time violations, while polarity correction circuits can invert signal logic to fix polarity reversals, allowing defect correction through parameter modification rather than redesign
2Productivity
If defects are detected late in the design cycle, then scan testing can be performed, but correction requires time-consuming mask revisions
Solution Approach 1:
The patent incorporates programmable circuitry during the initial synthesis stage, preparing the scan chains with built-in defect correction capabilities. This preliminary action allows defects to be detected and corrected without requiring time-consuming mask revisions later in the design cycle, as the correction functionality is already embedded in the circuit
Solution Approach 2:
The patent uses configurable memory cells to store correction patterns that can be loaded into the programmable circuitry. Instead of physically revising masks, the correction information is copied into memory cells and programmed into the circuit, enabling rapid defect correction without time-consuming physical redesign
3Ease of repair
If programmable circuitry is added to correct scan-chain defects, then defect correction capability is enabled, but circuit complexity increases
Solution Approach 1:
The patent designs the programmable circuitry to serve multiple functions: the same configurable memory cells and programmable delay elements can correct different types of defects (hold-time violations, polarity reversals) depending on how they are programmed. This multi-functionality reduces the need for separate dedicated correction circuits for each defect type, thereby limiting the increase in circuit complexity
Data Source
AI summary
In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.