Programmable SCR ESD Protection Circuit
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Solution Overview
Problem
Existing semiconductor controlled rectifier (SCR) circuits for electrostatic discharge (ESD) protection face challenges in achieving low switching and holding voltages while maintaining reliability, as they often require high switching voltages, increase leakage current, or necessitate special processes, and can latch during normal operation, posing risks to the gate oxide.
Innovation Solution
A programmable SCR circuit is designed with a PNP and NPN bipolar transistor configuration, incorporating a programmable n-channel transistor and resistor combination to control holding voltage, and shallow trench isolation to program switching voltage, ensuring high failure threshold and low on-resistance, with an optional diode to further reduce switching voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lateral SCR is used for ESD protection, then the failure threshold is significantly improved, but the switching voltage is relatively high requiring avalanche conduction
Solution Approach 1:
The patent modifies the junction characteristics by changing doping parameters and junction depth to reduce the avalanche breakdown voltage. Specifically, the N- and P- regions are engineered with specific doping concentrations and depths to achieve lower switching voltage while maintaining ESD protection capability
Solution Approach 2:
The patent introduces an n-channel transistor with grounded gate as an intermediary element that works in conjunction with the SCR structure. This transistor mediates the switching process by providing an additional conduction path that reduces the required switching voltage of the SCR
2Stress or pressure
If the switching voltage is reduced by adding a grounded gate n-channel transistor, then the switching voltage is substantially lower, but reliability concerns arise due to possible gate oxide rupture
Solution Approach 1:
The patent designs the SCR structure with pre-engineered N- and P- regions that create favorable electric field distributions before the switching event occurs. This preliminary structural preparation ensures that the electric field at the gate-to-drain overlap region remains within safe limits even when the n-channel transistor is activated
Solution Approach 2:
The patent applies different doping concentrations and junction depths in specific regions of the SCR structure. The N- and P- regions are locally optimized to control electric field distribution, creating areas with different electrical properties that protect the gate oxide while enabling low switching voltage operation
3Stress or pressure
If secondary protection circuits such as isolation resistor and grounded gate transistor are added, then switching voltage is reduced, but leakage current increases during normal operation
Solution Approach 1:
The patent merges the ESD protection function and the low switching voltage function into a single integrated SCR structure with pre-engineered N- and P- regions. This eliminates the need for separate secondary protection circuits and their associated leakage currents, achieving both low switching voltage and low leakage current through the unified structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a high failure threshold and low on-resistance, preventing latching during ESD events and protecting the gate oxide, while allowing for programmable switching and holding voltages, enhancing reliability and operational safety.
Implementation Method 1
The SCR switches from the forward blocking region to a minimum holding voltage (Vh) and holding current (Ih) region 106. At switching voltage Vsw 104, the SCR switches from the forward blocking region to a minimum holding voltage
Implementation Method 2
A first transistor having a control terminal and having a first current path terminal coupled to the third heavily doped region and a second current path terminal coupled to the second terminal is arranged to control a holding voltage of the circuit
Implementation Method 3
A programmable n-channel transistor and resistor combination to control holding voltage
Data Source
AI summary
A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal (310) and a second terminal (308). A first lightly doped region (304) having a first conductivity type (N−) is formed on a second lightly doped region (314) having a second conductivity type (P−). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region (400) having the second conductivity type (P+) is formed at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region. A first transistor (316) having a control terminal and having a first current path terminal coupled to the third heavily doped region and a second current path terminal coupled to the second terminal is arranged to control a holding voltage of the circuit.