Programmable Slew Rate PLL for UPS Voltage Stability
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Solution Overview
Problem
Conventional phase-locked loop (PLL) systems lack precise control over the slew rate, as it is not linearly related to the bandwidth of the control filter and is typically a soft limit, leading to variations in the rate of change of frequency over time.
Innovation Solution
A programmable slew rate limited PLL system that includes a slew rate limiter to determine if the frequency is changing at a rate greater than a maximum slew rate, generating a lock indication signal to control the output angle information and ensure it follows the input signal only within predetermined conditions, thereby maintaining synchronization with the input signal while preventing excessive phase following during transient conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a control filter with specific bandwidth is used in a conventional PLL, then the PLL can follow frequency changes of the input signal, but the slew rate is not precisely controlled and varies over time
Solution Approach 1:
The invention segments the PLL into two independent loops: a high-bandwidth PLL for accurate frequency tracking and a low-bandwidth PLL for stable phase output. A slew rate limiter monitors the frequency output from the high-bandwidth PLL and controls when the low-bandwidth PLL should lock to it, thereby precisely controlling the slew rate without requiring complex filtering in a single loop.
Solution Approach 2:
The slew rate limiter acts as an intermediary between the high-bandwidth PLL and the low-bandwidth PLL. It monitors the frequency output and generates a lock indication signal that gates the phase output, mediating the transfer of frequency information while enforcing slew rate limits.
2Reliability
If the PLL follows the input signal phase closely, then synchronization is achieved, but excessive phase following occurs during transient conditions causing voltage quality issues
Solution Approach 1:
The system dynamically adjusts the phase following behavior based on operating conditions. During steady-state conditions, the low-bandwidth PLL locks to the high-bandwidth PLL output for accurate synchronization. During transient conditions, the slew rate limiter prevents the low-bandwidth PLL from locking, thereby limiting the phase following speed and preventing excessive phase changes that would cause voltage quality issues.
Solution Approach 2:
The slew rate limiter provides feedback by monitoring the frequency output from the high-bandwidth PLL and generating a lock indication signal. This feedback mechanism detects transient conditions and controls whether the low-bandwidth PLL should follow the input signal phase, thereby maintaining output signal quality during both steady-state and transient operations.
3Reliability
If a single PLL is used for frequency tracking, then the system is simple, but the slew rate is only a soft limit with variations over time
Solution Approach 1:
The invention segments the frequency tracking function into two specialized PLL circuits: a high-bandwidth PLL optimized for rapid frequency acquisition and tracking, and a low-bandwidth PLL optimized for stable phase output with controlled slew rate. This segmentation transforms the soft slew rate limit of a single PLL into a precise, controllable limit.
Solution Approach 2:
The system changes the bandwidth parameter of the PLL based on operating conditions. The high-bandwidth PLL operates with wide bandwidth for fast tracking, while the low-bandwidth PLL operates with narrow bandwidth for controlled slew rate. The slew rate limiter dynamically selects which PLL output to follow, thereby precisely controlling the effective slew rate of the system output.
Data Source
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AI summary
A system includes a first phase-locked loop (PLL) circuit, a slew rate limiter and a second PLL. The first PLL is configured to receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal. The slew rate limiter is configured to receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate. The second PLL is configured to receive the first signal from the slew rate limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output.