Programmable Stacked Processor for Synchronized Data-Stream Throughput
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Solution Overview
Problem
Existing computing systems, such as CPUs, GPUs, and TPUs, suffer from inefficiencies in executing algorithms with repetitive sequences and conditional branches due to their von Neumann architecture, leading to unsynchronized core execution and resource sharing, which is not optimal for high throughput applications like encryption, decryption, and cryptocurrency processing.
Innovation Solution
A computing system with a stack of Slice Processor Units (SPUs) that execute preloaded instructions in parallel, supporting conditional branches through skip counts and multiple instruction tracks, allowing simultaneous execution of algorithm steps without fetching instructions from memory, thereby increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If von Neumann architecture with sequential instruction fetching is used, then general-purpose computing versatility is achieved, but throughput efficiency deteriorates due to one-at-a-time execution
Solution Approach 1:
The processor is divided into multiple pipeline stages (fetch, decode, execute, memory access, write-back) that process different instruction components simultaneously. Each stage performs a specific function, allowing multiple instructions to be in different phases of execution at the same time, thereby increasing throughput without requiring a completely different architectural approach.
2Productivity
If multiple processor cores are used, then computing power increases, but execution synchronization deteriorates due to independent instruction sequences
Solution Approach 1:
Multiple processor cores are merged into a single unified execution unit that processes instructions in a synchronized manner. The unified execution unit ensures that all cores execute the same instruction sequence at the same time, maintaining execution synchronization while still providing parallel processing capability for improved computing power.
3Adaptability or versatility
If instruction looping is used for repeated operations, then program flexibility is maintained, but execution time increases due to sequential rereading
Solution Approach 1:
The fetch stage pre-fetches and buffers instruction bytes before they are needed by subsequent stages. This preliminary action allows the decode and execute stages to proceed without waiting for sequential instruction fetching, reducing execution time while maintaining the ability to handle repeated operations through the pipeline.
4Device complexity
If resource sharing between cores is implemented, then device complexity is reduced, but resource idle time increases due to unsynchronized execution
Solution Approach 1:
The pipeline architecture ensures continuous processing by keeping all stages actively working at all times. While one instruction is being fetched, another is being decoded, and yet another is being executed, eliminating idle time. Resource sharing is implemented in a way that maintains this continuous flow, with shared resources being accessed in a synchronized manner that prevents idle periods.
Data Source
AI summary
A computing machine has a plurality of slice processing units (SPUs) coupled in a specific order from a first SPU to a last SPU, each SPU configured to perform a single instruction of a specific algorithm on an incoming value and to pass a resulting output value to a next SPU in the specific order. Values are retrieved from a memory unit by a direct memory access (DMA) controller and passed as input to the first SPU in the specific order, and each value passed begins a new performance of the algorithm executed in parallel with previously submitted values. Each SPU in each clock cycle performs its instruction and passes its result to the next SPU. A result for the algorithm is thus produced in each clock cycle. The SPUs are part of an application specific integrated circuit (ASIC) and may be programmed with instructions.