Software Programmable Hardware State Machines for In-Field Bug Correction
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Solution Overview
Problem
As processor complexity increases, detecting and correcting hardware bugs in-field becomes increasingly difficult, often resulting in costly recalls due to bugs being detected by customers during application use, rather than during design verification.
Innovation Solution
The implementation of software programmable hardware state machines that detect specific sequences of instructions causing errors and prevent unwanted changes in the processor's architectural state by using a programmable mask register and fix register to generate control signals for actions such as stalling instructions or generating exceptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional design verification methods (simulation, emulation, formal verification) are used, then verification thoroughness may be improved, but development time and cost increase significantly
Solution Approach 1:
The patent implements preliminary action by pre-programming the shadow PC with alternative instruction sequences that correspond to potentially buggy instruction patterns. Before execution, the system prepares detection and correction mechanisms by loading mask registers with buggy instruction patterns and shadow PC with safe alternative sequences, enabling proactive bug prevention rather than reactive detection
Solution Approach 2:
The patent introduces an intermediary mechanism - the shadow program counter and associated control logic - that mediates between the potentially buggy main instruction stream and the processor execution unit. This intermediary monitors instruction patterns, detects problematic sequences, and redirects execution to safe alternative instructions without requiring complete re-verification of the processor design
2Reliability
If hardware bugs are detected during customer application use, then real-world reliability data is obtained, but financial losses and customer inconvenience occur due to recalls
Solution Approach 1:
The patent applies beforehand cushioning by embedding bug detection and correction capabilities directly into the processor hardware before deployment. The shadow PC mechanism acts as a cushion that absorbs potential execution errors by providing alternative instruction sequences, preventing bugs from causing harmful effects in the first place rather than relying on post-deployment recalls
Solution Approach 2:
The patent implements feedback mechanisms where the control logic continuously monitors the instruction stream, compares it against known buggy patterns in mask registers, and immediately responds by redirecting execution through the shadow PC when problematic patterns are detected. This real-time feedback loop enables continuous reliability improvement without requiring product recalls
3Adaptability or versatility
If software programmable hardware state machines are added to detect and prevent errors, then in-field bug correction capability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the shadow PC mechanism to handle multiple types of bugs and instruction patterns through a single unified structure. The mask registers can be programmed with various buggy patterns, and the shadow PC can provide different alternative instruction sequences, making the system versatile against multiple error types without requiring separate detection mechanisms for each bug class
Solution Approach 2:
The patent uses copying by creating a shadow (copy) of the program counter that mirrors the main PC's functionality but points to alternative instruction sequences. This shadow copy enables bug correction without fundamentally altering the main processor structure, as the shadow PC can be programmed independently to handle various error scenarios
Data Source
AI summary
The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in architectural state from occurring as a result of execution of a specific sequence of instruction types. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The desired action may be preventing the dispatch of a next instruction, flushing a pipeline, clearing an instruction fetch buffer, generating an exception etc. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register.