Programmable Switch Hardware Architecture for Data Center Congestion Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current data center network routing systems face high processor overhead, processing latency, and compatibility issues due to reliance on software-based systems and limited protocol support, while FPGA platforms are difficult to program and expensive.

Innovation Solution

A programmable switch with a hardware architecture integrated into a printed circuit board, utilizing a programmable chip set that can route data packets based on flexible fields and support full line rate forwarding, incorporating a TCAM table for efficient packet matching and congestion control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software based routing systems are used, then routing flexibility is improved, but processor overhead and processing latency increase

Engineering Contradiction:

Improverouting flexibilityVSAvoidprocessing latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent replaces software-based routing processing with a hardware-based switching chip that performs packet matching and forwarding operations in hardware. This substitution eliminates the need for CPU intervention in packet forwarding, thereby reducing processor overhead and processing latency while maintaining routing flexibility through programmable packet field matching capabilities.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If FPGA platforms are used, then routing performance is improved, but programming difficulty and implementation cost increase

Engineering Contradiction:

Improverouting performanceVSAvoidprogramming difficulty

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent employs a switching chip that can be programmed via a server, offering a more accessible and cost-effective alternative to FPGA platforms. The chip provides full line rate forwarding capability and supports various forwarding schemes while being easier to program and implement compared to FPGA solutions.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Ease of operation

If OpenFlow switches are used, then protocol handling is simplified, but protocol compatibility and versatility are limited

Engineering Contradiction:

Improveprotocol handlingVSAvoidprotocol compatibility

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The switching chip is designed with universal packet matching capabilities that support multiple forwarding schemes including Destination Address, Source Routing, and Tag-based forwarding. This multi-functionality allows the system to handle various protocols and forwarding methods, providing broad protocol compatibility while maintaining ease of operation through centralized server-based programming.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Speed

If hardware architecture is implemented, then processing speed is improved, but device complexity increases

Engineering Contradiction:

Improveprocessing speedVSAvoiddevice complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent divides the routing system into two distinct components: a hardware switching chip responsible for high-speed packet matching and forwarding, and a server-based control system handling programming and configuration. This segmentation allows the hardware component to focus on speed-critical operations while the server manages complexity, thereby achieving high processing speed without excessive device complexity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9590922B2Programmable and high performance switch for data center networks

Publication Date: 2017.03.07 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

This application describes routing packets from a source server to a plurality of ports of a switch. The switch is programmed by the control server and is used to direct incoming data packets to one or more ports of the switch in a manner that reduces congestion of incoming data packets to a destination server. Further, the control server queries congestion information from the switch, and then sends congestion notification back to the source server to either increase or decrease the amount of data being sent to the destination server.