Programmable Sync Pulse Generator for Clock Domain Crossing
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Solution Overview
Problem
Conventional synchronizer circuitry using phase-locked loops (PLLs) is inadequate for synchronizing data transfer across clock domain boundaries due to lack of phase detection and drift tolerance, leading to timing-related data errors.
Innovation Solution
A programmable sync pulse generator and method that employs phase detection circuitry to sample clock signals, validate coincident edges with skew tolerance, and generate synchronization pulses in both clock domains, ensuring low latency and drift tolerance across clock domain boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loops (PLLs) are used for synchronizing data transfer across clock domain boundaries, then clock frequency relationships can be maintained, but phase detection capability and drift tolerance are insufficient leading to timing-related data errors
Solution Approach 1:
The patent segments the synchronization function into distinct modules: phase detection circuitry that samples clock signals to determine coincident edges, validation circuitry that validates edges based on skew tolerance, and sync generation circuitry that produces synchronization pulses. This segmentation allows each module to optimize for its specific function, with phase detection achieving precise timing measurement independent of PLL limitations.
Solution Approach 2:
The patent introduces an intermediary phase detection mechanism that samples both clock signals and identifies coincident edges as a reference point. This intermediary detection method mediates between the two clock domains, providing a reliable reference that neither PLL nor direct connection can achieve alone, thereby improving phase detection precision and data transfer reliability.
2Loss of time
If conventional PLL-based synchronizer circuitry is used, then clock frequency relationships are maintained, but latency is high and drift tolerance is insufficient
Solution Approach 1:
The phase detection circuitry performs preliminary sampling of clock signals to determine coincident edges before data transfer occurs. The validation circuitry pre-validates edges based on skew tolerance, and the sync generation circuitry prepares synchronization pulses in advance. This preliminary action sequence reduces synchronization latency by eliminating PLL acquisition time while maintaining drift tolerance through continuous edge validation.
Solution Approach 2:
The patent implements dynamic skew tolerance validation where the validation circuitry continuously adapts to clock skew variations within tolerance limits. This dynamic approach allows the system to accommodate frequency drift and timing variations without requiring re-synchronization, providing both low latency and high drift tolerance adaptability that static PLL configurations cannot achieve.
3Device complexity
If synchronization is implemented without phase detection capability, then device complexity is reduced, but timing-related data errors increase
Solution Approach 1:
The patent extracts the phase detection function from the traditional PLL architecture and implements it as a separate, dedicated phase detection circuitry. This extracted approach uses simple sampling and coincidence detection logic rather than complex PLL feedback mechanisms, reducing overall device complexity while improving data transfer reliability through accurate phase measurement and drift tolerance validation.
Data Source
AI summary
A programmable sync pulse generator and sync pulse generation method are operable in a clock synchronizer to effectuate data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. A phase detection circuitry is operable to sample the first clock signal with the second clock signal to determine coincident edges of the first and second clock signals. Validation circuitry is operable to validate the coincident edges based upon skew tolerance between the first and second clock signals and to generate a valid edge signal responsive thereto. Sync generation circuitry, responsive to the valid edge signal, is operable to generate synchronization pulses in the first clock domain and synchronization pulses in the second clock domain.