Programmable System Arbiter with Dynamic Priority Registers
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Solution Overview
Problem
Existing system arbitration schemes for embedded controllers are distributed, making it difficult to change the system priority order and require centralized management to accommodate new peripherals like DMA channels, while also needing backward compatibility with legacy components.
Innovation Solution
A programmable system arbiter with priority registers for CPU, arbiter clients, and interrupt types, allowing dynamic programming of priority orders based on operating modes and interrupt types, and protected by a LOCK/UNLOCK mechanism, enabling flexible and scalable arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a distributed arbitration scheme is used in embedded controllers, then each component can independently manage its own arbitration logic, but the system becomes difficult to modify and lacks flexibility when changing priority orders or accommodating new peripherals
Solution Approach 1:
The patent merges the arbitration logic from multiple distributed components into a single centralized programmable system arbiter. This consolidation allows the entire priority order to be managed and modified through a unified programming interface, enabling flexible reconfiguration of arbitration priorities without changing the underlying hardware structure. The centralized arbiter can accommodate new peripherals and change priority orders simply by updating the priority register values.
2Adaptability or versatility
If a centralized arbitration scheme is implemented to accommodate new peripherals like DMA channels, then system-wide priority management becomes possible, but backward compatibility with legacy components becomes difficult to maintain
Solution Approach 1:
The patent implements a dynamic priority assignment mechanism where the programmable system arbiter can be configured through software to assign different priority levels to various components. This dynamic configuration allows the system to maintain backward compatibility with legacy components by assigning them appropriate priority values in the priority registers, while simultaneously supporting new peripherals like DMA channels. The arbitration behavior adapts to different system requirements without requiring hardware changes.
3Ease of operation
If priority registers are made programmable for each arbiter client and operating mode, then dynamic priority assignment becomes possible, but the number of registers and configuration complexity increases
Solution Approach 1:
The patent implements a universal priority register structure where a single set of programmable priority registers can serve multiple arbiter clients and different operating modes. Instead of requiring separate dedicated registers for each client and mode, the same priority registers can be programmed to control arbitration for different components depending on the current operating mode. This multi-functional approach reduces the total number of registers while maintaining the capability for dynamic priority assignment across various scenarios.
Data Source
AI summary
A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.