Programmable Test Clock Generation for ASIC Fault Detection
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Solution Overview
Problem
As semiconductor device geometries shrink, timing-related at-speed faults caused by manufacturing defects and design margins become increasingly common, making it challenging to effectively test and diagnose faults in application-specific integrated circuits (ASICs).
Innovation Solution
A clock signal characterization circuit within the ASIC characterizes the clock signal and generates a programmable testing clock signal that replicates the operative clock signal, allowing for subsystem testing and subsequent modification to match or vary from the original characterization for fault detection and analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods are used, then testing simplicity is maintained, but detection precision of timing-related faults deteriorates
Solution Approach 1:
The patent creates a test clock signal that copies the characteristics of the operational clock signal by measuring parameters such as skew, jitter, and phase relationships. This copied test clock signal is then used to activate faults in the same way the operational clock signal does, enabling precise detection of timing-related faults without requiring complex external testing equipment.
Solution Approach 2:
The ASIC performs self-testing by using its own internal clock signal characterization circuitry to generate test clock signals. The system measures its own clock parameters and uses those measurements to create test signals that can detect faults within the same clock distribution network, eliminating the need for external testing systems.
2Area of moving object
If geometric dimensions are reduced, then device integration is improved, but reliability deteriorates due to increased timing faults
Solution Approach 1:
The patent implements feedback by measuring the actual clock signal parameters (skew, jitter, phase) and using these measurements to generate test clock signals. This feedback loop allows the system to detect timing-related faults caused by reduced geometry, enabling identification of defects that arise from manufacturing variations and design margins in smaller devices.
Data Source
AI summary
A clock signal within an application-specific integrated circuit (ASIC) is characterized while operating a subsystem. Subsequently, also on the ASIC, a testing clock signal is generated, based on the characterization of the operative clock signal, for purposes of testing the subsystem operating according to the testing clock signal instead of the clock signal. The ASIC includes a clock signal characterization circuit configured to characterize a clock signal within the ASIC; a programmable testing clock signal generator configured for being programmed based on said characterization of the clock signal, and for generating a test clock signal based on its said programming; and the subsystem tested when operating according to the testing clock signal instead of the clock signal.