Programmable Test Engine for Emerging Memory Technologies
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Solution Overview
Problem
Conventional built-in self-test (BIST) engines implement fixed test patterns, lacking programmability, which limits their flexibility and effectiveness in characterizing and debugging emerging memory technologies.
Innovation Solution
A programmable characterization-debug-test engine (PCDTE) is developed, featuring an instruction memory, configuration memory, and a controller that configures counters and data registers, allowing for customizable test patterns and operations, including read/write accesses and loop manipulation, to efficiently test memory technologies with varying parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fixed-pattern BIST engines are used, then the device complexity is low, but the adaptability and versatility are insufficient for emerging memory technologies
Solution Approach 1:
The BIST engine is designed with programmable counters and data registers that can be configured through configuration memory to perform multiple test functions. The same hardware structure can generate different test patterns (e.g., sequential, inverted, random) and support various memory types by loading different configuration values, eliminating the need for multiple dedicated test engines.
Solution Approach 2:
The counter structures are made dynamically configurable through control signals that can change their behavior during operation. Counters can be programmed to increment, decrement, or load specific values based on configuration memory contents, allowing the test engine to adapt its counting sequence and pattern generation dynamically rather than being fixed at design time.
2Adaptability or versatility
If programmable counters and data registers are added to enable customizable test patterns, then the adaptability improves, but the gate count and device complexity increase
Solution Approach 1:
Multiple functional components are merged into unified structures. The counters are designed to share common control logic and configuration interfaces, and data registers are integrated with the counter outputs to form a unified test pattern generation unit. This reduces the total gate count compared to having separate dedicated components for each function.
Solution Approach 2:
Instead of changing the hardware structure to achieve different test patterns, the invention changes the operational parameters of existing components through configuration memory. By programmably setting counter initial values, increment/decrement directions, and register data values, the system achieves high adaptability without adding significant hardware complexity.
3Adaptability or versatility
If multiple configurable counters are implemented to support various memory addressing schemes, then the versatility for testing different memory configurations improves, but the device complexity increases
Solution Approach 1:
The addressing function is segmented across multiple independent but identical counter modules. Each counter can be independently configured to handle different address dimensions (row, column, bank, etc.), and they work together through a unified control structure. This modular segmentation allows flexible combination to support various memory addressing schemes without requiring a completely different structure for each memory type.
4Reliability
If the BIST engine is made programmable with instruction memory and configuration memory, then the characterization and debugging capability improves, but the ease of manufacture decreases due to increased programming requirements
Solution Approach 1:
The instruction memory and configuration memory are programmed during the manufacturing process itself, before the product reaches the customer. Test patterns, counter configurations, and operational parameters are pre-loaded into the memory structures as part of the fabrication process, eliminating the need for complex post-manufacturing programming and simplifying the manufacturing workflow.
Data Source
AI summary
A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters. The PCDTE may transmit information off of the chip to exercise transmit/receive circuitry of the chip.