Programmable Timing for Peak Current Mode Power Converters
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Solution Overview
Problem
Peak current mode controlled power converters face stability issues and sub-harmonic oscillations, particularly above 50% duty cycle, and require precise timing of PWM waveforms to prevent shoot-through in power converters like synchronous buck converters.
Innovation Solution
The implementation of programmable timing in digital integrated circuits using timer counters to generate PWM waveforms, allowing for adjustable dead-times between switch operations based on load conditions and operating parameters, thereby preventing simultaneous switching of power converter switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If peak current mode control is used to achieve fast response and simplicity, then control speed and circuit simplicity are improved, but stability deteriorates above 50% duty cycle due to sub-harmonic oscillations
Solution Approach 1:
The patent applies preliminary action by implementing slope compensation that proactively adjusts the peak current reference before instability can occur. The compensation ramp is added to the current reference signal in advance, preventing sub-harmonic oscillations before they develop, thereby maintaining stability while preserving the fast response characteristics of peak current mode control.
2Device complexity
If fixed timing is used for PWM generation, then circuit complexity is reduced, but adaptability deteriorates as dead-time cannot be adjusted for different load conditions
Solution Approach 1:
The patent implements dynamics by making the dead-time programmable and adjustable based on operating conditions. The timer counter can be configured with different prescaler values and comparison values through digital control, allowing the dead-time to dynamically adapt to varying load conditions, input voltage ranges, and switching frequencies without requiring complex external circuitry.
3Reliability
If precise timing control is implemented to prevent shoot-through, then reliability is improved, but device complexity increases due to additional timing control circuitry
Solution Approach 1:
The patent applies merging by integrating the timing control functionality directly into the PWM generator block. The timer counter, prescaler, and comparison logic are combined within the existing PWM generation circuitry, eliminating the need for separate external timing components. This unified approach ensures precise timing control for shoot-through prevention while minimizing additional device complexity.
4Stability of the object's composition
If slope compensation is applied to maintain stability above 50% duty cycle, then stability is improved, but manufacturing precision requirements increase for accurate ramp generation
Solution Approach 1:
The patent replaces traditional analog ramp generation circuitry with a digital timer counter-based slope compensation mechanism. Instead of relying on precision analog components to generate the compensation ramp, the system uses digital counting and comparison operations that are inherently more robust to manufacturing variations. The slope compensation is achieved through programmed counter values rather than physical ramp circuits, significantly reducing manufacturing precision requirements.
Data Source
AI summary
An apparatus and a method for a programmable timing in digital integrated circuits implementing peak current mode controlled power converters are disclosed. The programmable dead-time is implemented by means implemented in hardware, software, and combination of hardware and software, carrying out setting a second timer value; setting a third timer value with respect to the second timer value; detecting a reset event; reloading a second counter from a current timer value to the second timer value upon detecting the reset event; resetting a second pulse width modulated waveform amplitude from a second amplitude value to a first amplitude value upon detecting the reset event; and setting a first pulse width modulated waveform from a first amplitude value to a second value upon the second counter reaching a third value.