Programmable Traffic Management Engine Offloads CPU
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Solution Overview
Problem
Current data center traffic management services rely heavily on CPU resources for packet scheduling, shaping, and policing, leading to high CPU utilization and reduced quality of service, especially in high-speed line-rate cloud architectures, where existing off-the-shelf NICs and switches lack programmability and customization.
Innovation Solution
A programmable traffic management engine with non-programmable hardware components generating predefined features and programmable hardware components executing customizable network scheduling algorithms, allowing for flexible deployment on high-speed platforms and reducing CPU burden by offloading traffic management tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traffic management services are provided by software applications executing on CPUs, then traffic management functionality is achieved, but CPU utilization increases and processing power for other tasks is reduced
Solution Approach 1:
The patent extracts traffic management services from the CPU software execution environment and implements them in dedicated hardware components within the NIC. This extraction moves the traffic management functionality out of the CPU's responsibility, allowing the CPU to focus on other tasks while the hardware handles packet scheduling, shaping, and policing independently.
Solution Approach 2:
The patent introduces a hardware-based traffic management engine as an intermediary between the network interface and the CPU. This intermediary handles traffic management operations in hardware, reducing the need for CPU intervention and thereby preserving CPU processing power for other computational tasks.
2Productivity
If traffic management services are moved to hardware to reduce CPU burden, then CPU processing power is preserved, but existing off-the-shelf NICs lack programmability and customization
Solution Approach 1:
The patent implements a dynamic, reconfigurable traffic management engine that can be programmed and customized through a configuration interface. The hardware components are designed to be adaptable, allowing network operators to modify scheduling algorithms and traffic management parameters without requiring physical hardware changes, thus providing both hardware efficiency and software-like flexibility.
Solution Approach 2:
The patent creates a universal traffic management hardware platform that can perform multiple traffic management functions (scheduling, shaping, policing) and support various algorithms. This multi-functional design allows a single hardware device to replace multiple specialized functions, providing both the efficiency of hardware and the versatility of programmability.
3Speed
If line-rate switches support traffic management services on ASICs, then processing speed is maintained, but algorithm selection is limited to predefined options
Solution Approach 1:
The patent implements a dynamic configuration capability that allows the traffic management algorithms to be changed and customized at runtime. The hardware is designed to accept configuration data that defines scheduling algorithms and parameters, enabling the system to adapt to different traffic management requirements while maintaining line-rate processing performance through hardware acceleration.
Data Source
AI summary
Examples herein describe a programmable traffic management engine that includes both programmable and non-programmable hardware components. The non-programmable hardware components are used to generate features that can then be used to perform different traffic management algorithms. Depending on which traffic management algorithm the PTM engine is configured to do, the PTM engine may use a subset (or all) of the features to perform the algorithm. The programmable hardware components in the PTM engine are programmable (e.g., customizable) by the user to perform a selected algorithm using some or all of the features provided by the non-programmable hardware components.