Programmable Trigger Logic for Cycle-Accurate SoC Debugging
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Solution Overview
Problem
The increasing complexity of System on a Chip (SoC) devices makes it challenging to accurately debug and identify the source of issues during SoC bring-up and debugging, as existing design-for-debug architectures struggle to capture cycle-accurate information in a time-efficient manner due to clock cycle leaks and overall clock skews.
Innovation Solution
A method involving a programmable trigger signal that stops the input clock and root clock of the SoC, allowing for the collection and output of cycle-accurate information from functional blocks, using clock halt counters to determine the accurate state of surrounding blocks at the time of failure, thereby enhancing debugging capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional design-for-debug architectures are used to observe internal nodes of the SoC, then debugging capability is provided, but cycle-accurate information cannot be captured due to clock cycle leaks and overall clock skews
Solution Approach 1:
A debug module is introduced as an intermediary component between the functional blocks and the external debugging interface. This debug module includes a trigger generator/sequencer that receives trigger signals and generates clock stop signals to halt the root clock, thereby eliminating clock cycle leaks and skew issues that would otherwise prevent accurate state capture at the time of triggering events
2Measurement precision
If the root clock is stopped to capture accurate state information, then measurement precision is improved, but productivity decreases due to additional clock stopping and state collection overhead
Solution Approach 1:
The debug module is pre-configured with trigger conditions and the trigger generator/sequencer is prepared to automatically generate clock stop signals when triggering events occur. This preliminary setup eliminates the need for manual intervention during debugging, allowing the system to automatically capture accurate state information at the precise moment of triggering events, thereby maintaining high debugging efficiency while ensuring measurement precision
3Adaptability or versatility
If more functional blocks are monitored to improve debugging coverage, then debugging capability is enhanced, but device complexity increases
Solution Approach 1:
The debug module is designed as a universal debugging interface that can monitor multiple functional blocks through a single centralized trigger generator/sequencer. Instead of implementing separate debugging mechanisms for each functional block, this multi-functional debug module can selectively trigger and capture states from any monitored functional block, thereby enhancing debugging coverage without proportionally increasing device complexity
Data Source
AI summary
In one embodiment, cycle-accurate information may be collected by stopping an input clock associated with a functional block of a SoC using a programmable trigger signal. The programmable trigger signal may also stops a root clock of the SoC. Cycle-accurate information may be collected regarding the functional block and at least one other functional block of the SoC at the time of the programmable trigger signal. The collected information may be outputted and used to debug the SoC in a time-efficient manner.