Programmable Tunnel Thermionic Mode FET for Low Power
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Solution Overview
Problem
Current semiconductor transistors face challenges in reducing power consumption due to the inability to lower supply voltage below 1 V, leading to increased energy requirements and heating issues, as the Boltzmann limit restricts sub-threshold slope and ON/OFF current ratios, and existing solutions like ferroelectric materials or tunnel FETs either fail to achieve both low OFF state currents and high ON state currents simultaneously or suffer from slow switching times and hysteresis loss.
Innovation Solution
A programmable tunnel thermionic mode FET with an asymmetric dual-gate architecture that independently controls the height and width of the Schottky barrier, allowing operation in both tunneling and thermionic modes, enabling sub-threshold swing less than 60 mV/dec and high ON state currents, by varying the back-gate and top-gate voltages to switch between modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOSFET scaling is continued to increase transistor density, then functionality is enhanced, but power consumption increases exponentially due to inability to reduce supply voltage below 1 V
Solution Approach 1:
The patent changes the fundamental conduction mechanism parameter from thermionic emission to quantum tunneling by engineering Schottky barriers at source-channel and drain-channel interfaces. This parameter change enables operation at sub-1V supply voltages while maintaining acceptable ON currents, thereby reducing power consumption as P=CV²f
Solution Approach 2:
The patent introduces dynamic control of barrier height and width through dual-gate voltage modulation. By dynamically adjusting gate voltages, the device can switch between tunneling and thermionic modes, optimizing performance for different operating conditions and enabling low-power operation
2Loss of energy
If tunnel FET is used to reduce power consumption, then OFF state current is reduced, but switching time increases and hysteresis loss occurs
Solution Approach 1:
The patent introduces dynamic control of barrier height and width through dual-gate voltage modulation. By dynamically adjusting gate voltages, the device can switch between tunneling and thermionic modes, optimizing performance for different operating conditions and enabling low-power operation
Solution Approach 2:
The patent segments the control function into two independent gates: one controlling barrier height and the other controlling barrier width. This segmentation allows independent optimization of tunneling efficiency and switching speed, reducing the trade-off between low OFF current and fast switching
3Use of energy by moving object
If ferroelectric material is used to achieve low sub-threshold slope, then power consumption is reduced, but switching speed decreases and hysteresis loss increases
Solution Approach 1:
The patent changes the conduction mechanism from thermionic emission dominated by Boltzmann statistics to quantum tunneling dominated by wave mechanics. This fundamental parameter change achieves sub-60mV/dec sub-threshold slope without relying on ferroelectric materials, thereby maintaining fast switching speeds and avoiding hysteresis losses
4Power
If Schottky barrier height is reduced to increase ON current, then ON state current increases, but OFF state current also increases
Solution Approach 1:
The patent segments the barrier control into two independent dimensions: barrier height controlled by one gate and barrier width controlled by the other gate. This segmentation enables independent optimization where barrier height can be reduced for high ON current while barrier width is simultaneously maintained for low OFF current, achieving high ION/IOFF ratio
Solution Approach 2:
The patent applies different electrical conditions locally at the source and drain contacts through the dual-gate structure. By creating asymmetric local conditions, the device achieves favorable barrier characteristics at each interface, enabling high ON current through optimized tunneling while maintaining low OFF current through effective barrier blocking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced power consumption by achieving low OFF state currents and high ON state currents in the same device, compatible with scaled supply voltages and high-frequency switching, addressing the limitations of existing technologies in achieving both regimes simultaneously.
Implementation Method 1
The channel layer forms a Schottky barrier at points of contact with the source electrode and the drain electrode
Implementation Method 2
allowing operation in both tunneling and thermionic modes
Implementation Method 3
allowing operation in both tunneling and thermionic modes
Data Source
AI summary
The field effect transistor (FET) of the present subject matter comprises a bottom gate electrode, a bottom gate dielectric provided on the bottom gate electrode, a channel layer provided on the bottom gate dielectric. A top portion comprising a source electrode, a drain electrode, a top gate electrode provided, and a top dielectric layer is provided on the channel layer. The channel layer forms Schottky barriers at points of contact with the source and the drain electrode. A back-gate voltage varies a height and a top-gate voltage varies a width of the Schottky barrier. The FET can be programmed to work in two operating modes-tunnelling (providing low power consumption) and thermionic mode (providing high performance). The FET can also be programmed to combine the tunnelling and thermionic mode in a single operating cycle, yielding high performance with low power consumption.