Progressive Random Access Scan Circuitry for VLSI Testing
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Solution Overview
Problem
Current methods for testing very large scale integrated (VLSI) circuits, such as serial-scan and random access scan, face challenges including high power consumption, heat dissipation issues, long test application times, and significant hardware overhead, which can lead to incorrect responses and yield loss.
Innovation Solution
The Progressive Random Access Scan (PRAS) system, which uses a scan cell with pass transistors and reduced control lines, operates as a Static Random Access Memory cell in test mode, allowing for efficient addressing and reduced overhead, and is configured in a grid structure to minimize routing and hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial scan is used for testing VLSI circuits, then hardware overhead is reduced, but test application time increases and power consumption increases
Solution Approach 1:
The scan chain is divided into multiple segments or groups, allowing parallel test application to different segments. This segmentation enables simultaneous testing of multiple circuit portions, reducing overall test application time while maintaining the serial scan architecture's low hardware overhead benefits
Solution Approach 2:
The scan architecture dynamically switches between serial scan mode for low overhead and parallel scan mode for reduced test time. The system can adaptively select the operating mode based on test requirements, combining the advantages of both approaches
2Device complexity
If serial scan is used for testing VLSI circuits, then hardware overhead is reduced, but power consumption increases
Solution Approach 1:
Instead of shifting test data through the entire scan chain for every test vector, the invention applies partial scan actions only to the necessary segments. This reduces unnecessary switching activity and power consumption while maintaining effective test coverage
Solution Approach 2:
The scan operation uses periodic clocking with idle periods between test applications. During idle periods, the scan chain is held stable, reducing dynamic power consumption from continuous switching while maintaining test capability
3Loss of time
If random access scan is used for testing VLSI circuits, then test application time is reduced, but hardware overhead increases
Solution Approach 1:
The circuit is divided into segments with selective random access capability. Only critical segments require full random access hardware, while other segments use simpler access mechanisms, reducing overall hardware overhead while maintaining reduced test application time
Solution Approach 2:
The scan architecture provides universal access capabilities that can operate in both serial and random access modes. The same hardware infrastructure supports multiple testing strategies, eliminating the need for separate dedicated random access hardware and reducing overall overhead
4Loss of time
If random access scan is used for testing VLSI circuits, then test application time is reduced, but hardware overhead increases
Solution Approach 1:
The circuit is divided into segments with selective random access capability. Only critical segments require full random access hardware, while other segments use simpler access mechanisms, reducing overall hardware overhead while maintaining reduced test application time
Solution Approach 2:
The scan architecture provides universal access capabilities that can operate in both serial and random access modes. The same hardware infrastructure supports multiple testing strategies, eliminating the need for separate dedicated random access hardware and reducing overall overhead
Data Source
AI summary
A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one or more pass transistors and a flip flop. The scan cell may be one of a plurality of addressable scan cells in one or more grids for testing the integrated circuit. For example, the scan cells may be arranged in a single grid or may be partitioned into two or more grids. The scan cell may be used for reliability testing or for performance testing. The PRAS cell for performance testing may be staged, with a first pattern applied and then a second pattern applied. For example, one section of the scan cell may operate using a clock cycle of Φ1 and another section of the PRAS cell may operate using a clock cycle of Φ2 which is different from Φ1.