3D Semiconductor Memory Structure With Projecting Layer Overlap
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and capacity while maintaining efficient data storage capabilities, particularly in three-dimensional memory structures.
Innovation Solution
A semiconductor memory device with a specific configuration that includes a semiconductor layer, multiple interconnect layers, and memory pillars, along with distinct members and interconnect structures, enhancing the integration and capacity of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted for higher integration, then the storage capacity and integration density are improved, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The semiconductor layer is divided into multiple regions with different doping types (first doped region and second doped region), and the interconnect structure is segmented into multiple layers (first interconnect layer, second interconnect layer) with distinct functions. This segmentation allows complex 3D memory structures to be built through manageable, modular fabrication steps, reducing overall manufacturing complexity while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from planar 2D memory structures to three-dimensional vertical structures by stacking multiple interconnect layers and doped regions in the depth direction. Memory pillars extend vertically through multiple interconnect layers, enabling higher integration density and storage capacity by utilizing the third dimension (depth) for additional storage cells without increasing footprint area.
2Quantity of substance
If multiple interconnect layers and memory pillars are added for higher integration, then the memory capacity increases, but the device structure becomes more complex
Solution Approach 1:
The first and second doped regions serve multiple functions: they act as charge storage regions for memory operation, provide electrical connectivity between different interconnect layers, and form selective contact structures with the memory pillars. This multi-functionality reduces the need for separate dedicated structures, thereby increasing memory capacity without proportionally increasing structural complexity.
Solution Approach 2:
Memory pillars are nested within the three-dimensional structure formed by stacked interconnect layers and doped regions. The pillars extend vertically through multiple horizontal layers, with each layer containing smaller functional elements within the larger 3D architecture. This nested arrangement maximizes memory capacity within a compact volume while maintaining organized, manageable structural hierarchy.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a semiconductor layer arranged above a substrate in a first direction; a first interconnect layer between the substrate and the semiconductor layer; a second interconnect layer arranged adjacent to the first interconnect layer in a second direction; a plurality of memory pillars; and a first member between the first interconnect layer and the second interconnect layer. The semiconductor layer has, on a side of a second surface facing a first surface in contact with the first member, a first projecting portion projecting in the first direction and overlapping a part of an area in the first direction, the area being provided with the first interconnect layer and the first member.