PROM Cell Insulating Layer Layout for Predictable Breakdown
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Solution Overview
Problem
Existing programmable read-only memories, such as fuse-type PROMs, face challenges in predictability and variability of binary value storage due to unpredictable insulation layer breakdown and potential damage during manufacturing processes, leading to inconsistent threshold values between memory cells.
Innovation Solution
A programmable read-only memory cell design featuring a semiconductor substrate with specific doping regions and an insulating layer structure, where the insulating layer is intentionally damaged in a predictable location by a controlled current, allowing for reliable binary value storage by measuring resistance to determine the stored data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulating layer is damaged by electrical breakdown to store binary values in fuse-type PROM, then memory programming is achieved, but the breakdown location is unpredictable and variability between cells increases
Solution Approach 1:
The patent applies local quality by creating a specifically doped region (region 18) with higher dopant concentration than the surrounding well (region 16), forming a localized area with different electrical properties. This heavily doped region serves as a predetermined breakdown location, ensuring that when electrical breakdown occurs during programming, it happens consistently at the same location across all memory cells, thereby improving both reliability and manufacturing precision
Solution Approach 2:
The patent implements preliminary action by pre-doping the semiconductor well to create region 18 with elevated dopant concentration before the memory programming process. This preliminary structural modification ensures that the insulating layer breakdown will occur at the predetermined location when programming is performed, eliminating variability and ensuring consistent binary value storage across all cells
2Productivity
If manufacturing processes are used to create memory cells, then production is achieved, but damage to the insulating layer occurs leading to inconsistent threshold values
Solution Approach 1:
By creating a localized heavily doped region (region 18) with distinct electrical characteristics, the patent ensures that breakdown occurs predictably in this specific area during manufacturing. This local quality modification protects the overall manufacturing process while ensuring consistent threshold values, as the breakdown is confined to the predetermined region rather than occurring randomly throughout the insulating layer
Solution Approach 2:
The patent converts the potentially harmful effect of manufacturing-induced damage to the insulating layer into a beneficial outcome by designing the structure so that any breakdown occurs at the predetermined heavily doped region (region 18). This predetermined breakdown location, which might initially seem like a vulnerability, actually ensures consistent threshold values and reliable binary value storage by preventing random breakdown locations that would cause variability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures consistent and predictable binary value storage by controlling the breakdown location of the insulating layer, reducing variability and manufacturing-induced damage, thus enhancing the reliability of programmable read-only memory cells.
Implementation Method 1
the insulating layer 22 comprises a first, or central, portion 22a and a second, or peripheral portion 22b... During a programming step of the memory cell, a current flows through the cell between layer 24 and region 14, passing through layer 22 and region 18. The value of the current is sufficiently high to crack, or break, the material of layer 22
Data Source
Figure 1~2
Figure 3
AI summary
The present description relates to a programmable read-only memory cell (10) comprising a first insulating layer (22) located between a semiconductor casing (12) and a second conductive or semiconductor layer (24), the first insulating layer (22) comprising a peripheral part (22b) and a central part (22a), the peripheral part (22b) having a thickness greater than the thickness of the central part (22a).