Proof-Tree Structure for Parallel Sequential Equivalence Checking
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Solution Overview
Problem
The process of sequential equivalence checking (SEC) for semiconductor circuit designs is time-consuming and complex due to the need to compare multiple potential equivalent sub-circuit pairs at a register transfer level, making it difficult to verify and optimize circuit designs efficiently.
Innovation Solution
A proof-tree structure is used to verify child-proofs in parallel, updating parent-proofs and ultimately the root-proof's equivalency status, reducing the time required for verification and optimization by restructuring the SEC process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential equivalence checking is performed by comparing multiple potential equivalent sub-circuit pairs at register transfer level, then verification completeness is improved, but verification time and system complexity increase
Solution Approach 1:
The verification process is divided into hierarchical levels: the circuit design is partitioned into multiple sub-circuit pairs, each verified independently as a separate unit. This segmentation allows parallel processing of sub-circuit verifications while maintaining overall verification completeness, thereby reducing total verification time without sacrificing reliability
Solution Approach 2:
The patent introduces a hierarchical dimension to the verification process by organizing sub-circuit verifications into a tree structure with root proofs, intermediate proofs, and leaf proofs. This dimensional organization enables parallel execution of verifications at different hierarchical levels, transforming a sequential time-consuming process into a concurrent multi-level operation that maintains completeness while reducing time loss
2Measurement precision
If sequential equivalence checking compares multiple potential equivalent sub-circuit pairs, then verification accuracy is improved, but device complexity increases
Solution Approach 1:
The complex verification system is segmented into modular components including sub-circuit partitioning modules, equivalence checking modules, and proof management modules. Each module handles a specific aspect of verification, making the overall complex system manageable and maintainable while preserving verification accuracy through systematic processing
Solution Approach 2:
The patent introduces intermediate proofs as mediator structures that connect root proofs to leaf proofs in the verification hierarchy. These intermediate proofs serve as aggregation points that consolidate verification results from multiple sub-circuits, simplifying the complexity management by providing structured intermediate representation without compromising the accuracy of final verification results
Data Source
AI summary
Disclosed is a technology for parallelized design verification of two circuit designs at a register transfer level. A plurality of potential equivalent sub-circuit pairs is identified from the circuit designs to create a proof-tree structure. The proof-tree structure includes a root-proof, a plurality of parent-proofs downchain of said root-proof and a plurality of child-proofs downchain of at least one of the parent-proofs. Each one of the child-proofs is associated with a first equivalency status of one of the potential equivalent sub-circuit pairs. The parent-proofs are associated with second equivalency statuses dependent upon the first equivalency statuses of downchain child-proofs. The root-proof is associated with a third functional equivalency status of the two circuit designs dependent upon the second equivalency statuses of downchain parent-proofs. This Abstract is not intended to limit the scope of the claims.