Property Quality Verification for Digital Circuit Error Detection
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Solution Overview
Problem
Current methods for verifying the quality of digital circuit designs are inefficient, as they rely on selective and resource-intensive approaches that do not guarantee detection of all errors, especially due to the large number of possible input patterns and the disparity between simulation and real circuit run times.
Innovation Solution
A method is introduced to determine the quality of a quantity of properties describing a machine by identifying interrelated properties that unambiguously determine output values at specific points in time, allowing for systematic verification and adjustment of property sets to ensure comprehensive error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation is used as the principal method for functional verification, then errors can be detected by comparing output patterns with expectations, but the large disparity between simulation run time and real circuit run time limits the number of input patterns that can be tested, leaving many errors undetected
Solution Approach 1:
The patent replaces traditional simulation-based verification with a formal verification approach using property checkers that mathematically prove circuit correctness. Instead of mechanically simulating countless input patterns, the system uses formal methods to verify properties, achieving both high error detection capability and fast verification speed.
Solution Approach 2:
The patent changes the fundamental parameter of verification from exhaustive input pattern simulation to systematic property-based checking. By transforming the verification approach from temporal simulation to logical property validation, the system overcomes the speed limitation while maintaining or improving error detection accuracy.
2Productivity
If property checkers are used to verify critical behavioural associations, then verification speed improves significantly, but only selective properties are checked based on engineer intuition, leaving many errors undetected
Solution Approach 1:
The patent makes the property verification system universal by automatically generating comprehensive property sets that cover all possible errors, not just critical ones selected by engineers. The system serves multiple functions: generating properties, checking them systematically, and ensuring complete error detection across the entire circuit behavior.
Solution Approach 2:
The verification system performs self-service by automatically generating the complete set of properties to be checked without relying on engineer intuition. The system independently identifies what needs to be verified and executes the verification, eliminating the subjectivity and incompleteness of manual property selection.
3Measurement precision
If the quantity of properties describing circuit behavior is increased to improve error detection, then verification quality improves, but the complexity of the verification environment and resource requirements increase
Solution Approach 1:
The patent segments the verification process into distinct automated components: property generation, property checking, and quality assessment. This segmentation manages complexity by organizing the verification environment into modular, systematically processed stages rather than a monolithic complex system.
Solution Approach 2:
The patent introduces feedback mechanisms where the property checker systematically evaluates generated properties and provides information about verification quality. This feedback loop enables automatic adjustment and optimization of the verification process, managing complexity through intelligent control rather than brute-force expansion.
Data Source
AI summary
A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P0, P1, . . . Pn) of the form Pi=(forall t. Ai(t)=>Zi(t)), wherein Ai(t) present an initial state and Zi(t) a target state for a corresponding property and at least one initial state Ai is dependant on internal signals and including a step for checking whether at least one aspect of the input/output behavior of the machine described by the properties, which cannot be derived from an individual property Pi, is described to such an accurate extent that one property Q exists, which represents this aspect without being dependant on the internal signals. The procedure is capable of providing a measurement and can particularly be used in the verification and specification of circuits.