Protected CSP Pad Structure for Corrosion Resistance
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Solution Overview
Problem
The pads in integrated circuit (IC) dies are susceptible to corrosion and damage during the chip-scale packaging process, which can lead to increased contact resistance and reliability issues in CMOS image sensors, affecting the functionality and performance of the sensors.
Innovation Solution
A protected chip-scale packaging (CSP) pad structure is implemented, where a bridge connects two pads, with only one pad exposed for testing and subsequently cut, keeping the other pad covered and thus protected from damage, allowing for reliable external link formation without corrosion concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If pads are exposed for testing during the chip-scale packaging process, then testing functionality is enabled, but pads become susceptible to corrosion and damage
Solution Approach 1:
The pad structure is divided into two distinct pads: a first pad that is exposed for testing purposes and a second pad that remains covered by the passivation layer to prevent corrosion. This segmentation allows each pad to serve its specific function while protecting the integrity of the pad used for packaging connections.
Solution Approach 2:
Different regions of the pad structure have different properties: the first pad region is exposed to enable testing access, while the second pad region maintains passivation layer coverage to prevent corrosion. This local differentiation of protection levels allows simultaneous testing capability and corrosion protection.
2Reliability
If pads are covered by passivation layer, then corrosion protection is provided, but testing access is blocked
Solution Approach 1:
The passivation layer is segmented to cover only the second pad while leaving the first pad exposed. This selective coverage enables the first pad to be accessed for testing without compromising the corrosion protection on the second pad.
Solution Approach 2:
The passivation layer provides localized protection: it is removed from the first pad area to enable testing access while maintaining coverage over the second pad area to provide corrosion protection during packaging operations.
3Ease of manufacture
If contact resistance increases due to corrosion, then bonding performance deteriorates, but manufacturing process remains simple
Solution Approach 1:
The second pad is pre-protected by the passivation layer before the packaging process begins. This preliminary protection prevents corrosion from occurring during subsequent manufacturing steps, ensuring low contact resistance and high bonding performance are maintained throughout the process.
Data Source
AI summary
A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.