Protected Fin Etching to Prevent GAA Source/Drain Merger
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Solution Overview
Problem
In semiconductor manufacturing, the fabrication of gate-all-around (GAA) FETs faces challenges such as epitaxial material merger between adjacent fin structures during the formation of strained source/drain regions, leading to reduced fabrication yield and potential damage to isolation regions.
Innovation Solution
A method is developed to protect the isolation region during the etch process for forming source/drain cavities, ensuring that epitaxial growth does not merge between adjacent fin structures, by forming a spacer layer and using a blocking layer to prevent epitaxial material growth into trenches, thereby maintaining the integrity of the isolation material and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the etch process is performed to form source/drain cavities, then the source/drain regions can be formed, but epitaxial material merges between adjacent fin structures and isolation regions are damaged
Solution Approach 1:
A spacer layer is introduced as an intermediary protective structure between adjacent fin structures. This spacer layer prevents direct contact and merging of epitaxial material from neighboring fins, while also protecting the isolation regions during the etch process. The spacer acts as a physical barrier that maintains the integrity of isolation regions while allowing source/drain cavity formation.
2Ease of manufacture
If the etch process is performed to form source/drain cavities, then the source/drain regions can be formed, but epitaxial material merges between adjacent fin structures
Solution Approach 1:
The spacer layer serves as a protective intermediary that maintains precise separation between epitaxial materials from adjacent fin structures. During the etch process and subsequent epitaxial growth, the spacer prevents lateral merging of epitaxial material, ensuring that each fin structure's source/drain regions remain distinct and properly defined.
Solution Approach 2:
The spacer layer is formed in advance before the etch process and epitaxial growth. This preliminary protective structure is prepared on the fin structures to ensure that when the etch process occurs and epitaxial material is deposited, the separation between adjacent structures is already established and protected, preventing any merging that would compromise manufacturing precision.
3Reliability
If the gate structure surrounds the fin on three surfaces, then better gate control is achieved, but the bottom part of the channel is far from the gate electrode and not under close control
Solution Approach 1:
Instead of having the gate electrode surround the fin from the sides and top, the invention inverts the approach by placing the gate electrode at the bottom of the fin structure. This bottom-gate configuration allows the gate to control the channel from underneath, achieving full surround control including the previously unreachable bottom portion of the channel, thereby eliminating the control gap while maintaining structural simplicity.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first fin structure and a second fin structure, wherein an isolation region is located between the fin structures, and wherein a space is located between the fin structures and above the isolation region; depositing a blocking layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the blocking layer is located above the first fin structure and the second fin structure, and wherein a lower portion of the blocking layer fills the space located between the first fin structure and the second fin structure; removing the upper portion of the blocking layer; and while the lower portion of the blocking layer remains over the isolation region, performing an etch process to recess the first fin structure and the second fin structure.