Protected Transmission Gate for LVDS Receiver Aging Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit IO pins configured for single-ended or low-voltage differential signaling (LVDS) experience unequal aging stress due to different signal patterns, leading to performance issues when reconfigured for higher-bandwidth LVDS data rates, especially as transistors operate at increasingly lower voltages, risking electrical overstress.
Innovation Solution
Incorporating higher-voltage transmission gate circuitry with multiple lower-voltage transistors that receive protection voltages to prevent junction voltage exceeding limits, ensuring the LVDS receiver is protected from unequal signals while blocking higher-voltage single-ended signals or passing LVDS signals, thereby maintaining the junction voltage within safe limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IO pins are configured for single-ended signaling with different static signal values, then each pin can operate independently with different input/output patterns, but the transistors connected to different pins experience different levels of aging stress and BTI stress, leading to performance degradation when reconfigured for LVDS
Solution Approach 1:
A transmission gate is introduced as an intermediary component between the IO pins and the LVDS receiver. This transmission gate selectively connects or disconnects the IO pins from the LVDS receiver based on the operating mode. When IO pins are configured for single-ended signaling, the transmission gate blocks the connection, preventing unequal aging stress from affecting the LVDS receiver. When reconfigured for LVDS, the transmission gate enables the connection, allowing the receiver to function normally without accumulated stress effects.
Solution Approach 2:
The transmission gate is configured to block the connection between IO pins and LVDS receiver before the aging stress can accumulate during single-ended operation. This preliminary protective action ensures that when the IO pins are later reconfigured for LVDS, the receiver starts from a fresh state without degraded performance, effectively preventing the aging stress issue before it occurs.
2Reliability
If transmission gate circuitry is used to block higher-voltage single-ended signals from reaching the LVDS receiver, then the receiver is protected from electrical overstress, but the transmission gate requires higher voltage ratings than the receiver transistors can handle
Solution Approach 1:
The transmission gate is segmented into two separate transmission gates: a first transmission gate connected to the IO pins with higher voltage ratings to handle single-ended signaling voltages, and a second transmission gate connected to the LVDS receiver with lower voltage ratings matching the receiver's voltage requirements. This segmentation allows each transmission gate to be optimized for its specific voltage level, protecting the receiver from electrical overstress while avoiding the need for the entire transmission path to withstand high voltages.
Solution Approach 2:
Different parts of the transmission path are assigned different voltage handling capabilities based on their local requirements. The first transmission gate near the IO pins has high voltage rating to block single-ended signals, while the second transmission gate near the receiver has low voltage rating appropriate for the receiver. This local quality differentiation resolves the contradiction by matching voltage ratings to actual operational requirements at each location.
Data Source
AI summary
Integrated circuit devices, methods, and circuitry for selectively blocking a voltage signal on receiver circuitry to reduce or eliminate unequal aging on the receiver circuitry. A device may include a first input/output (IO) pin to receive a first voltage and a second IO pin to receive a second voltage. The device may include a differential signal receiver that includes a first terminal coupled to the first IO pin and a second terminal coupled to the second IO pin. Transmission gate circuitry may selectively block the first voltage or the second voltage from being applied to the differential signal receiver. The transmission gate circuitry may include transistors having a lower junction voltage limit than the first voltage or the second voltage, or both.