Protected Level Shifter Topology for Full-Swing PVT-Stable Output
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Solution Overview
Problem
Conventional level shifters in system-on-chip (SoC) devices are limited by their inability to generate output voltages that reach the minimum and maximum levels of other voltage domains due to voltage protection constraints, leading to variations caused by process, voltage, and temperature (PVT) fluctuations, and require large transistors that increase size and reduce speed.
Innovation Solution
A level shifter design comprising a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator, which uses reference and bias voltages to generate output voltages that can reach the desired voltage levels without relying on large transistors, thereby reducing size and increasing speed by minimizing PVT variations' impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large-sized transistors are implemented in the voltage protection circuit to reduce PVT variations, then the stability of output voltages is improved, but the area occupied by the level shifter increases and the speed of operation degrades
Solution Approach 1:
The patent changes the operating parameters of the transistors by introducing reference voltages and bias voltages that allow small transistors to operate in an optimized regime. The protection circuit uses reference voltages to dynamically adjust the operating point, enabling compact transistors to maintain stability without requiring large dimensions.
Solution Approach 2:
The patent introduces reference voltages and bias voltages as intermediary elements that mediate between the input signals and the output voltages. These intermediary voltages allow the protection circuit to control the operation of compact transistors, achieving stable output voltage generation without requiring large transistor sizes.
2Reliability
If large-sized transistors are implemented in the voltage protection circuit to reduce PVT variations, then the stability of output voltages is improved, but the speed of operation degrades
Solution Approach 1:
The patent optimizes the speed parameter by changing the operating conditions of the transistors through reference voltages and bias voltages. This allows compact transistors to operate at higher speeds while maintaining stability, eliminating the need for large transistor sizes that would slow down operation.
Solution Approach 2:
The patent introduces dynamic control through reference voltages that adapt to PVT variations in real-time. This dynamic adjustment allows the protection circuit to maintain stability without relying on large transistor sizes, thereby preserving high-speed operation.
3Reliability
If voltage protection circuit is added to protect transistors from high voltages, then the reliability of transistor operation is improved, but the output voltages are unable to reach minimum and maximum voltage levels of the other voltage domain
Solution Approach 1:
The patent introduces reference voltages as intermediary elements between the protection circuit and the output stage. These reference voltages enable the protection circuit to safeguard transistors while allowing the output voltages to reach the full range of the target voltage domain through the output generator circuit.
Solution Approach 2:
The patent segments the level shifter into distinct functional blocks: protection circuit, output generator, and pull-down/pull-up circuits. This segmentation allows the protection circuit to independently protect transistors while the output generator independently ensures full voltage range output, resolving the conflict between protection and voltage range.
4Device complexity
If conventional level shifter design is used, then the circuit structure is simple, but the output voltages vary due to PVT variations
Solution Approach 1:
The patent implements feedback mechanisms through reference voltages that are compared with actual output voltages. This feedback allows the protection circuit and output generator to dynamically adjust and compensate for PVT variations, maintaining consistent output voltages without significantly increasing circuit complexity.
Solution Approach 2:
The patent introduces reference voltages as intermediary elements that mediate between the input signals and output voltages. These reference voltages serve as stable benchmarks that compensate for PVT variations, maintaining output consistency while keeping the overall circuit structure relatively simple.
Data Source
AI summary
A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.