Protected Memory and Cache Remapping for Sensitive Data Execution

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Solution Overview

Problem

Micro-architectural data movements in information handling systems are vulnerable to attacks, allowing malicious users to infer secret data and steal sensitive information, particularly during execution and data transfer.

Innovation Solution

Implementing a protected execution zone across system memory and CPU cache, using security descriptors and volatile protected execution zones to limit access to sensitive data based on context-specific processes, and remapping memory to create secure zones that follow data movements through the execution path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory is allocated from a secure zone with access blocking using security descriptors, then data security is improved, but device complexity increases

Engineering Contradiction:
Improvedata securityVSAvoidmemory management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory space is segmented into secure zones and non-secure zones, with each zone having distinct access control policies. Security descriptors are used to define access permissions for different processes to specific memory segments, enabling fine-grained security control without protecting entire memory spaces uniformly.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Security descriptors act as intermediary structures between processes and memory resources. These descriptors contain access control information that mediates process requests to memory, allowing the system to enforce security policies without requiring complex direct process-memory permission management.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If firmware remapped memory and cache address lines are used to execute sensitive data, then data protection is improved, but processing speed may deteriorate

Engineering Contradiction:
Improvedata protectionVSAvoiddata processing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system performs preliminary remapping of memory addresses and cache lines during system initialization or before sensitive operations. By pre-configuring the address translation tables and cache associativity settings, the system avoids runtime overhead while maintaining protection, as the remapping structure is established in advance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory remapping and cache configuration are dynamically adjusted based on the sensitivity of the data being processed. The system can switch between different address translation modes and cache policies depending on whether sensitive or non-sensitive data is active, optimizing performance for each case while maintaining security when needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12566894B2Micro-architectural data protection
Publication Date: 2026.03.03 DELL PROD LP
  • US12566894B2 patent drawing
  • US12566894B2 patent drawing
  • US12566894B2 patent drawing

AI summary

An information handling system in response to detecting sensitive data, gets a memory allocated to the sensitive data from a secure zone of a dual in-line memory module. The system also blocks processes from access to the memory allocated to the sensitive data from the secure zone using security descriptors and access the sensitive data from the secure zone of the dual in-line memory module based on the security descriptors. In addition, the system executes the sensitive data in a firmware remapped memory and cache address line.