Protected Pipeline Modes With Clearing for DSP Interrupts

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Solution Overview

Problem

Existing digital signal processors (DSPs) face challenges in efficiently processing real-time data streams due to memory bandwidth and scheduling issues, particularly in unprotected pipelines where instruction dependencies can lead to pipeline hazards and inefficient handling of interrupts.

Innovation Solution

Implementing a method and processor architecture that allows switching between protected and unprotected execution modes, using capture queues to manage pipeline hazards and enable efficient interrupt handling, ensuring correct execution by storing partial results in capture queues and restoring them after interrupts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If unprotected pipeline mode is used to increase processing speed, then instruction execution rate improves, but pipeline hazards occur due to instruction dependencies

Engineering Contradiction:

Improveinstruction execution rateVSAvoidpipeline hazard occurrence

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The processor dynamically switches between protected and unprotected pipeline modes based on interrupt conditions. The pipeline protection mechanism is activated only when interrupts are pending, allowing the system to maximize performance in normal operation while ensuring correctness during interrupt handling.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the protection parameter of the pipeline dynamically. By modifying the pipeline protection state from protected to unprotected mode (and vice versa), the system adapts to different operational requirements, balancing performance and reliability based on interrupt status.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If protected pipeline mode is used to ensure correct instruction execution, then pipeline hazards are prevented, but processing speed decreases

Engineering Contradiction:

Improveinstruction execution correctnessVSAvoidinstruction execution rate

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Instead of maintaining protected pipeline mode continuously, the system applies protection only partially—specifically when interrupts are pending. This reduces the overall impact on performance while still providing necessary protection during critical interrupt handling periods.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If pipeline clearing is performed to handle interrupts, then interrupt handling correctness improves, but processing time increases

Engineering Contradiction:

Improveinterrupt handling correctnessVSAvoidinterrupt handling time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Instead of clearing the entire pipeline unconditionally, the system performs partial pipeline clearing only for the necessary portions when interrupts occur. This minimizes the time loss while still ensuring correct interrupt handling by clearing only the affected pipeline stages.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The system discards incomplete instructions in the pipeline when interrupts occur, but recovers by switching to unprotected mode for subsequent instructions that do not depend on the interrupted operations. This allows the system to handle interrupts correctly while minimizing the impact on overall processing time.

Inventive Principle:

Principle #34Discarding and recovering

Data Source

PatentUS20250291597A1Entering protected pipeline mode with clearing

Publication Date: 2025.09.18 TEXAS INSTRUMENTS INC

AI summary

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.