Protecting Liner for Integrated Circuit Interlayer Dielectric
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Solution Overview
Problem
The interlayer dielectric in integrated circuits is vulnerable to damage during the formation of recesses for embedded electrical interconnects, leading to potential degradation and issues like high contact resistance and time-dependent dielectric breakdown, which existing protective measures, such as electrically-conductive barrier layers, often fail to address effectively before metal interconnect formation.
Innovation Solution
A protecting liner with at least two layers having different etch rates in various etchants is formed in the recess over the embedded electrical contact, allowing for selective etching to expose the contact while protecting the sides, enabling additional processing without damaging the interlayer dielectric and facilitating the formation of an embedded electrical interconnect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an electrically-conductive barrier layer is formed in the recess prior to metal interconnect formation, then the metal interconnect is sealed from the exposed portions of the interlayer dielectric, but the interlayer dielectric remains vulnerable to damage from additional processing steps
Solution Approach 1:
A protecting liner is formed in the recess immediately after recess formation and before any additional processing steps. This preliminary protective measure shields the interlayer dielectric from damage during subsequent processing such as silicide formation, while still allowing the processing steps to be completed. The protecting liner is removed after it has served its protective function, enabling the formation of the electrically-conductive barrier layer and metal interconnects without compromising the interlayer dielectric integrity.
2Reliability
If additional processing is conducted after recess formation to lower contact resistance, then contact resistance between embedded electrical contacts and metal interconnects is reduced, but the interlayer dielectric is degraded and damaged
Solution Approach 1:
The protecting liner acts as an intermediary layer between the additional processing steps and the interlayer dielectric. It allows processing such as silicide formation to proceed while preventing harmful effects from reaching the interlayer dielectric. The protecting liner is selectively removed over the embedded electrical contacts to enable low-resistance electrical connection, while remaining in place to protect the surrounding interlayer dielectric from damage.
3Device complexity
If the interlayer dielectric is formed directly over embedded electrical contacts, then the structure is simplified, but interfaces between layers become vulnerable to metal ion flow and time dependent dielectric breakdown
Solution Approach 1:
The protecting liner is segmented into different portions with different fates: it remains in place to protect the interlayer dielectric interfaces from metal ion flow and TDDB, while being selectively removed over the embedded electrical contacts to enable electrical connection. This segmentation allows the same layer to serve multiple protective and functional roles, maintaining simplified layer structure while enhancing interface integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects the interlayer dielectric from damage, maintains low contact resistance, and prevents metal ion flow, thereby enhancing the reliability and performance of integrated circuits by ensuring the integrity of the dielectric and electrical connections.
Implementation Method 1
A protecting liner is formed in the recess and over the exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants.
Implementation Method 2
a metal silicide layer may be formed in the embedded electrical contact by blanket depositing a thin layer of silicide-forming metal on the ILD and the embedded electrical contact in the recess followed by annealing to form the metal silicide layer
Data Source
AI summary
Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.