Semiconductor Package Protection Bar Warpage Reduction

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Solution Overview

Problem

The mismatch in coefficients of thermal expansion between semiconductor chip packages and their components leads to warpage during thermal cycles, causing stress on solder joints and potential electrical connection failures between the package and the printed circuit board.

Innovation Solution

A semiconductor package structure featuring a carrier substrate with an integrated circuit die encapsulated by a molding compound and equipped with solder balls on one surface and a thermosetting polymeric protection bar on the other, which counteracts warping forces and reduces stress on solder joints by providing mechanical support.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If materials with different coefficients of thermal expansion are used in the package structure, then functional requirements are met, but package warpage occurs during thermal cycles

Engineering Contradiction:
Improvematerial compatibilityVSAvoidpackage warpage
Core Design Contradiction:
Adaptability or versatilityVSShape

Solution Approach 1:

The patent introduces a protection bar with specific material properties (different from both the molding compound and substrate) at a localized position (between the molding compound and substrate). This local quality change allows different regions of the package to have optimized thermal expansion characteristics, counteracting warpage while maintaining overall material compatibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The protection bar is constructed from composite material comprising a core layer and an outer layer with different material properties. The core layer provides structural support while the outer layer matches the thermal expansion coefficient of adjacent materials, creating a composite structure that mitigates warpage through controlled differential expansion.

Inventive Principle:
Principle #40Composite materials

2Reliability

If protection bar is added to prevent warpage, then package reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protection bar is divided into multiple segments or layers (core layer and outer layer) that can be independently manufactured and characterized. This segmentation allows each layer to be optimized for specific functions while maintaining overall simplicity in the integration process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protection bar serves multiple functions simultaneously: it acts as a mechanical support to prevent warpage, provides thermal management by matching thermal expansion coefficients, and maintains electrical isolation. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The protection bar maintains package shape and reduces stress on solder joints, enhancing reliability by preventing damage from compressive and tensile stresses, ensuring stable electrical connections throughout thermal cycles.

Implementation Method 1

differences in coefficient of thermal expansion among a molding compound which forms the package body, a semiconductor chip which is made of silicon, and solder balls consisting of tin alloy, can cause separation of the materials during subsequent reliability testing

Methodology Applied
Scientific EffectThermal expansion mismatch: Thermal Expansion

Data Source

PatentUS7923852B2Semiconductor package structure with protection bar
Publication Date: 2011.04.12 NAN YA TECH
  • US7923852B2 patent drawing
  • US7923852B2 patent drawing
  • US7923852B2 patent drawing

AI summary

A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface.