Micro-Architectural Protection Table for Secure Page Walks
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Solution Overview
Problem
Current memory addressing schemes using paging are inefficient due to the high cost of accessing page tables, which are typically stored in main memory, leading to performance issues during virtual to physical address translations.
Innovation Solution
The processor extends page walks by introducing a micro-architectural protection table that manages permissions and attributes at a page-level granularity, allowing for efficient checks and actions during memory operations, utilizing a protection table management logic to access and modify permissions without incurring significant performance or hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If page tables are stored in main memory to enable virtual memory paging, then memory addressing flexibility is improved, but access time increases significantly
Solution Approach 1:
The patent pre-loads page table entries into the TLB (Translation Lookaside Buffer) before they are needed for address translation. By anticipating future page access patterns and loading translations in advance, the system reduces the time penalty associated with main memory access when page tables are needed, while maintaining the flexibility of virtual memory paging.
2Speed
If TLB is used to cache page translations, then address translation speed is improved, but hardware complexity increases
Solution Approach 1:
The patent makes the existing TLB structure serve dual purposes: it continues to function as a translation cache for address speedup while simultaneously acting as a security attribute cache. By storing both translation information and security attributes (such as permission bits, encryption keys, or access control data) in the same TLB entry structure, the system achieves enhanced functionality without proportionally increasing hardware complexity.
3Reliability
If security checks are enhanced during page walks, then system security is improved, but performance overhead increases
Solution Approach 1:
The patent performs security attribute validation during the page walk process itself, rather than as a separate subsequent step. By checking security attributes (such as permission bits, encryption requirements, or access control lists) while the page table is being traversed to obtain the translation, the system ensures security without adding a separate performance-critical validation phase that would increase overhead.
Data Source
AI summary
An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.