Protective Barrier Layer for Superconductor Circuit Fabrication

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Solution Overview

Problem

Current methods for fabricating superconducting qubits, such as electron beam lithography, are slow and prone to errors, limiting the production of reliable and scalable superconducting circuits needed for quantum computing and cryptography applications.

Innovation Solution

A method involving the use of a protective barrier layer formed from an organic spin-on material, cured at temperatures below 150°C, to protect the superconducting material during photolithography and etching processes, allowing for the formation of precise patterns in superconductor and Josephson junction structures without damaging the fragile qubit structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If electron beam lithography is used to fabricate superconducting qubits, then small feature sizes can be achieved, but production time becomes very long taking several hours to write a wafer

Engineering Contradiction:
Improvefeature sizeVSAvoidproduction time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The fabrication process is divided into multiple sequential lithography steps (first lithography step for base layer, second lithography step for mesa layer) rather than attempting to fabricate all features in a single step. This allows each step to use optimized lithography parameters and speeds up overall production while maintaining precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A protective barrier layer is deposited and cured before the lithography steps to protect the superconducting material layer during subsequent processing. This preliminary protective action enables faster etching and processing without risking damage to the qubit structures, thereby increasing productivity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If small samples are used with quick turn-around time, then production time is reduced, but the relative economies of scale that make volume semiconductor fabrication attractive are not exploited

Engineering Contradiction:
Improveturn-around timeVSAvoideconomies of scale
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The fabrication method is designed to be universally applicable to both small and large wafer sizes using standard silicon processing equipment. The process flow and lithography techniques can handle various wafer dimensions, allowing manufacturers to exploit economies of scale by processing larger wafers without sacrificing turn-around time efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The process parameters (such as lithography exposure conditions, etching parameters, and curing temperatures) are optimized to work across different sample sizes. This allows the same fabrication protocol to be applied whether processing small or large wafers, enabling economies of scale while maintaining quick turn-around times.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If standard silicon processing equipment is used to fabricate superconducting qubits, then manufacturing costs are reduced, but the fragile qubit structures may be damaged during processing

Engineering Contradiction:
Improvemanufacturing costVSAvoidqubit structure integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A protective barrier layer is deposited and cured before lithography and etching steps to protect the fragile superconducting qubit structures during processing. This preliminary protective measure enables the use of standard silicon processing equipment that would otherwise be too aggressive for qubit fabrication, reducing costs while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective barrier layer acts as an intermediary between the standard silicon processing equipment and the fragile qubit structures. It shields the qubits from damaging effects of lithography and etching processes while allowing the equipment to operate at standard parameters, thus enabling cost-effective manufacturing without compromising qubit integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Quantity of substance

If multiple samples need to be fabricated, then the fabrication process needs to be repeated, but this increases the likelihood of errors at any step in the process flow

Engineering Contradiction:
Improvenumber of samplesVSAvoidprocess error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The fabrication process is segmented into standardized, repeatable steps with clear intermediate states. Each lithography and etching step produces a well-defined intermediate structure that can be verified before proceeding to the next step, reducing error propagation when fabricating multiple samples.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protective barrier layer is temporarily introduced and then removed after serving its protective function during critical processing steps. This temporary protective measure can be discarded after use, allowing the same process flow to be reliably repeated for multiple samples without cumulative damage or error accumulation.

Inventive Principle:
Principle #34Discarding and recovering

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the reliable and efficient fabrication of superconducting circuits and Josephson junctions using standard silicon processing equipment, reducing manufacturing costs and minimizing errors, thereby facilitating the mass production of qubits.

Implementation Method 1

curing the protective barrier layer at a temperature of about 140° C. to about 150° C. for about 60 to about 120 seconds

Methodology Applied
Scientific EffectCuring:

Implementation Method 2

irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer

Methodology Applied
Scientific EffectPhotopolymerization: Photopolymerisation

Data Source

PatentUS8735326B2Methods of forming superconductor circuits
Publication Date: 2014.05.27 NORTHROP GRUMMAN SYSTEMS CORP
  • US8735326B2 patent drawing
  • US8735326B2 patent drawing
  • US8735326B2 patent drawing

AI summary

Methods of forming superconducting devices are disclosed. In one embodiment, the method can comprise depositing a protective barrier layer over a superconducting material layer, curing the protective barrier layer, depositing a photoresist material layer over the protective barrier layer and irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer. The method can further comprise etching the protective barrier layer to form openings in the protective barrier layer based on the opening pattern, etching the superconductor material layer based on the openings in the protective barrier layer to form openings in the superconductor material layer that define a first set of superconductor material raised portins and stripping the photoresist material layer and the protective barrier layer.