Protective Layer for Electronic Packaging Contact Stress
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Solution Overview
Problem
In high-density electronic packaging, terminal contacts and conductor wires are prone to damage due to stress accumulation from environmental changes and external forces, leading to reliability issues and increased costs with existing protective solutions.
Innovation Solution
A protective structure comprising a compressible macromolecule layer that covers the surrounding of conductor trace lines and via holes without contacting them, integrated with dielectric layers and a substrate to distribute stress and enhance protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protective cap is added to cover the chip and components, then the protection from contamination and exterior forces is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the protective function with the existing dielectric layer structure. The dielectric layer serves dual purposes: electrical insulation and mechanical protection against contamination and exterior forces, eliminating the need for separate protective caps and reducing manufacturing complexity.
Solution Approach 2:
The dielectric layer is designed to perform multiple functions simultaneously: providing electrical insulation between conductive elements, offering mechanical protection against contamination, and serving as a structural component in the packaging architecture. This multi-functionality reduces the overall number of components needed.
2Quantity of substance
If the space between electronic components is reduced to increase density, then the packaging density is improved, but the stress concentration on terminal contacts increases
Solution Approach 1:
The patent applies different material properties to different regions of the packaging structure. The dielectric layer uses materials with specific mechanical properties (such as lower modulus of elasticity) in regions where stress concentration occurs, while maintaining high density in other areas. This localized optimization allows high packaging density without excessive stress concentration.
Solution Approach 2:
The patent employs composite material structures combining different dielectric materials with varying mechanical and electrical properties. By strategically selecting and combining materials, the structure achieves both high packaging density and reduced stress concentration through the complementary properties of the composite system.
3Stress or pressure
If the dielectric layer material is selected with lower modulus of elasticity, then the stress on conductor trace lines is reduced, but the structural strength may be compromised
Solution Approach 1:
The patent uses composite dielectric layer structures where materials with lower modulus of elasticity are combined with other materials that provide structural strength. The composite system achieves both stress reduction for conductor protection and sufficient structural integrity through the synergistic properties of the combined materials.
Solution Approach 2:
Different regions of the dielectric layer use materials with optimized properties: regions adjacent to conductor trace lines use materials with lower modulus of elasticity to reduce stress, while other regions use materials with higher strength to maintain overall structural integrity. This spatial differentiation of material properties resolves the contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces stress on terminal contacts and conductor wires, improving reliability and reducing material costs by using a simpler manufacturing process applicable to various electronic package structures.
Implementation Method 1
The protecting layer has a material of compressible macromolecules and the protecting layer covers the chip incompletely
Data Source
AI summary
A structure for protecting electronic package contacts is provided. The structure includes at least an electronic contact mounted on a chip, a dielectric layer, a conductor trace line and a protective layer. The protective layer is used to prevent stresses from being gathered within electronic contacts on the chip through surroundingly covering the conductor trace line.