Selective Protective Layer for Interconnect Via Critical Dimension Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits (ICs) are scaled down, the increased density and reduced spacing between conductive features lead to increased capacitance, power consumption, and time delay, posing challenges in manufacturing techniques and device design to maintain performance.
Innovation Solution
A dual damascene process is used with a selective deposition of a protective layer on interconnect dielectric layers to reduce the critical dimension of interconnect vias, preventing damage and misalignment, and enhancing the reliability of the integrated chip by reducing capacitance between conductive features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between conductive features is reduced to increase density, then device density is improved, but capacitance increases leading to higher power consumption and time delay
Solution Approach 1:
The patent applies local quality by selectively depositing a protective layer only on specific surfaces (first surface of first interconnect dielectric layer and second surface of second interconnect dielectric layer) while leaving other surfaces unprotected. This localized protection enables closer spacing of conductive features in certain areas to reduce capacitance and power consumption, while maintaining adequate spacing in other areas where the protective layer prevents damage during etching operations.
2Manufacturing precision
If the critical dimension of interconnect vias is reduced to improve device density, then manufacturing precision is improved, but the risk of damage and misalignment increases
Solution Approach 1:
The patent implements preliminary action by depositing the protective layer on the interconnect dielectric layer surfaces before performing the etching process to form interconnect vias. This pre-deposited protective layer serves as a safeguard during the subsequent etching operations, preventing damage to the dielectric layer and ensuring accurate via formation with controlled critical dimensions, thereby reducing misalignment risks.
Solution Approach 2:
The protective layer acts as an intermediary between the etching process and the interconnect dielectric layer. It mediates the interaction by providing a protective barrier during etching, allowing precise via formation without directly exposing the dielectric layer to damaging etchants, thus maintaining both manufacturing precision and reliability.
3Reliability
If a protective layer is deposited on interconnect dielectric layers to prevent damage, then reliability is improved, but the critical dimension of interconnect vias increases
Solution Approach 1:
The protective layer is selectively applied only to specific surfaces of the interconnect dielectric layer where damage prevention is needed during etching, while leaving other areas unprotected or with different protection levels. This localized approach prevents unnecessary addition of protective material in via regions, thereby maintaining tight critical dimension control while still providing reliability benefits where the protective layer is applied.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the critical dimension of interconnect vias and wires, improving device density, reliability, and reducing capacitance, thereby enhancing the performance and lifespan of integrated chips.
Implementation Method 1
a protective layer is selectively deposited on the first and second interconnect dielectric layers
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via.