Selective Protective Layering for Smaller Interconnect Vias
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) are scaled down, the increased density and reduced spacing between conductive features lead to increased capacitance, power consumption, and time delay, posing challenges in manufacturing techniques and device design to maintain performance.
Innovation Solution
A dual damascene process is used with a selective deposition of a protective layer on interconnect dielectric layers to reduce the critical dimension of interconnect vias, preventing damage and misalignment, and maintaining reliability by using a protective layer with a slower etch rate than the etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between conductive features is reduced to increase density, then the element density is improved, but the capacitance increases leading to higher power consumption and time delay
Solution Approach 1:
A protective layer is deposited in advance on the dielectric layer before etching the interconnect via. This preliminary protective action prevents damage to the dielectric layer during subsequent etching processes, enabling tighter spacing between conductive features without compromising structural integrity, thereby increasing element density while controlling capacitance effects
2Use of energy by moving object
If the critical dimension of interconnect vias is reduced to decrease capacitance, then the power consumption is reduced, but the manufacturing precision and alignment become more difficult to maintain
Solution Approach 1:
The protective layer is deposited beforehand on the dielectric layer to establish a robust structural foundation before via etching. This preliminary reinforcement allows for precise via formation at smaller critical dimensions without compromising alignment accuracy, enabling reduced capacitance while maintaining manufacturing precision
Solution Approach 2:
The protective layer acts as a cushioning layer deposited in advance to absorb mechanical stress and prevent damage during etching processes. This beforehand cushioning enables the fabrication of smaller, more tightly spaced vias with better alignment precision while reducing capacitance between conductive features
3Reliability
If a protective layer is deposited on the dielectric layer to prevent damage, then the reliability is improved, but the critical dimension of interconnect vias increases
Solution Approach 1:
The protective layer is selectively deposited only on specific regions of the dielectric layer where via etching will occur, rather than uniformly across the entire structure. This localized protection maintains structural reliability during etching while minimizing the increase in critical dimension, as the protective material is confined to targeted areas
Solution Approach 2:
The protective layer is deposited with a thickness that provides sufficient protection during etching but is optimized to minimize its impact on the final via critical dimension. By applying partial protection only where needed and controlling the deposition thickness, structural reliability is improved without excessive increase in critical dimension
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the critical dimension of interconnect vias, improves alignment, and decreases capacitance, thereby enhancing the reliability and performance of integrated chips by minimizing damage to dielectric layers and reducing cross-talk between conductive features.
Implementation Method 1
selective deposition of a protective layer on interconnect dielectric layers
Implementation Method 2
protective layer with a slower etch rate than the etch stop layer
Data Source
AI summary
In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.